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文件名称:de1_t1

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    36.51mb
  • 已下载：
    0次
  • 提 供 者：
    guo***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

DE1的LED流水灯，数码管显示，可修改参数完成自定义的显示，有UART串口通信代码，VGA信号显示图片。-DE1 of the LED water lamp, LED display, you can modify the parameters to complete a custom show that UART serial communication code, VGA signal display pictures.
相关搜索： DE1 vga DE1 UART

(系统自动生成,下载前可以参看下载内容)

下载文件列表

de1_T1
de1_T1/Crt_clk_bps.v
de1_T1/Crt_clk_bps.v.bak
de1_T1/db
de1_T1/db/de1_t1.(0).cnf.cdb
de1_T1/db/de1_t1.(0).cnf.hdb
de1_T1/db/de1_t1.(1).cnf.cdb
de1_T1/db/de1_t1.(1).cnf.hdb
de1_T1/db/de1_t1.(2).cnf.cdb
de1_T1/db/de1_t1.(2).cnf.hdb
de1_T1/db/de1_t1.(3).cnf.cdb
de1_T1/db/de1_t1.(3).cnf.hdb
de1_T1/db/de1_t1.(4).cnf.cdb
de1_T1/db/de1_t1.(4).cnf.hdb
de1_T1/db/de1_t1.(5).cnf.cdb
de1_T1/db/de1_t1.(5).cnf.hdb
de1_T1/db/de1_t1.(6).cnf.cdb
de1_T1/db/de1_t1.(6).cnf.hdb
de1_T1/db/de1_t1.(7).cnf.cdb
de1_T1/db/de1_t1.(7).cnf.hdb
de1_T1/db/de1_t1.(8).cnf.cdb
de1_T1/db/de1_t1.(8).cnf.hdb
de1_T1/db/de1_t1.(9).cnf.cdb
de1_T1/db/de1_t1.(9).cnf.hdb
de1_T1/db/de1_t1.asm.qmsg
de1_T1/db/de1_t1.asm_labs.ddb
de1_T1/db/de1_t1.atom_map.rvd
de1_T1/db/de1_t1.cbx.xml
de1_T1/db/de1_t1.cmp.bpm
de1_T1/db/de1_t1.cmp.cdb
de1_T1/db/de1_t1.cmp.ecobp
de1_T1/db/de1_t1.cmp.hdb
de1_T1/db/de1_t1.cmp.kpt
de1_T1/db/de1_t1.cmp.logdb
de1_T1/db/de1_t1.cmp.rdb
de1_T1/db/de1_t1.cmp.tdb
de1_T1/db/de1_t1.cmp0.ddb
de1_T1/db/de1_t1.cmp2.ddb
de1_T1/db/de1_t1.cmp_merge.kpt
de1_T1/db/de1_t1.db_info
de1_T1/db/de1_t1.eco.cdb
de1_T1/db/de1_t1.eda.qmsg
de1_T1/db/de1_t1.eds_overflow
de1_T1/db/de1_t1.fit.qmsg
de1_T1/db/de1_t1.fnsim.hdb
de1_T1/db/de1_t1.fnsim.qmsg
de1_T1/db/de1_t1.hier_info
de1_T1/db/de1_t1.hif
de1_T1/db/de1_t1.lpc.html
de1_T1/db/de1_t1.lpc.rdb
de1_T1/db/de1_t1.lpc.txt
de1_T1/db/de1_t1.map.bpm
de1_T1/db/de1_t1.map.cdb
de1_T1/db/de1_t1.map.ecobp
de1_T1/db/de1_t1.map.hdb
de1_T1/db/de1_t1.map.kpt
de1_T1/db/de1_t1.map.logdb
de1_T1/db/de1_t1.map.qmsg
de1_T1/db/de1_t1.map_bb.cdb
de1_T1/db/de1_t1.map_bb.hdb
de1_T1/db/de1_t1.map_bb.logdb
de1_T1/db/de1_t1.merge.qmsg
de1_T1/db/de1_t1.pre_map.cdb
de1_T1/db/de1_t1.pre_map.hdb
de1_T1/db/de1_t1.rpp.qmsg
de1_T1/db/de1_t1.rtlv.hdb
de1_T1/db/de1_t1.rtlv_sg.cdb
de1_T1/db/de1_t1.rtlv_sg_swap.cdb
de1_T1/db/de1_t1.sgate_sm.rvd
de1_T1/db/de1_t1.sgdiff.cdb
de1_T1/db/de1_t1.sgdiff.hdb
de1_T1/db/de1_t1.sim.cvwf
de1_T1/db/de1_t1.sim.qmsg
de1_T1/db/de1_t1.sim.rdb
de1_T1/db/de1_t1.simfam
de1_T1/db/de1_t1.sld_design_entry.sci
de1_T1/db/de1_t1.sld_design_entry_dsc.sci
de1_T1/db/de1_t1.syn_hier_info
de1_T1/db/de1_t1.tan.qmsg
de1_T1/db/de1_t1.tis_db_list.ddb
de1_T1/db/de1_t1.tmw_info
de1_T1/db/de1_t1_global_asgn_op.abo
de1_T1/db/prev_cmp_de1_t1.asm.qmsg
de1_T1/db/prev_cmp_de1_t1.eda.qmsg
de1_T1/db/prev_cmp_de1_t1.fit.qmsg
de1_T1/db/prev_cmp_de1_t1.map.qmsg
de1_T1/db/prev_cmp_de1_t1.merge.qmsg
de1_T1/db/prev_cmp_de1_t1.qmsg
de1_T1/db/prev_cmp_de1_t1.sim.qmsg
de1_T1/db/prev_cmp_de1_t1.tan.qmsg
de1_T1/db/wed.wsf
de1_T1/de1_t1.asm.rpt
de1_T1/de1_t1.cdf
de1_T1/de1_t1.done
de1_T1/de1_t1.dpf
de1_T1/de1_t1.eda.rpt
de1_T1/de1_t1.fit.rpt
de1_T1/de1_t1.fit.smsg
de1_T1/de1_t1.fit.summary
de1_T1/de1_t1.flow.rpt
de1_T1/de1_t1.map.rpt
de1_T1/de1_t1.map.smsg
de1_T1/de1_t1.map.summary
de1_T1/de1_t1.merge.rpt
de1_T1/de1_t1.pin
de1_T1/de1_t1.pof
de1_T1/de1_t1.qpf
de1_T1/de1_t1.qsf
de1_T1/de1_t1.qws
de1_T1/de1_t1.sim.rpt
de1_T1/de1_t1.sof
de1_T1/de1_t1.tan.rpt
de1_T1/de1_t1.tan.summary
de1_T1/de1_t1.v
de1_T1/de1_t1.v.bak
de1_T1/de1_t1.vwf
de1_T1/de1_t1_nativelink_simulation.rpt
de1_T1/incremental_db
de1_T1/incremental_db/compiled_partitions
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.cmp.atm
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.cmp.dfp
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.cmp.hdbx
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.cmp.kpt
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.cmp.logdb
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.cmp.rcf
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.map.atm
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.map.dpi
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.map.hdbx
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.map.kpt
de1_T1/incremental_db/compiled_partitions/de1_t1.root_partition.merge_hb.atm
de1_T1/incremental_db/README
de1_T1/LEDG_Drive.v
de1_T1/LEDG_Drive.v.bak
de1_T1/pll_control.ppf
de1_T1/pll_control.qip
de1_T1/pll_control.v
de1_T1/pll_control_bb.v
de1_T1/pll_control_inst.v
de1_T1/pll_control_wave0.jpg
de1_T1/pll_control_waveforms.html
de1_T1/SEG7_LUT.v
de1_T1/SEG7_LUT_4.v
de1_T1/SEG7_LUT_4.v.bak
de1_T1/simulation
de1_T1/simulation/modelsim
de1_T1/simulation/modelsim/de1_t1.sft
de1_T1/simulation/modelsim/de1_t1.vo
de1_T1/simulation/modelsim/de1_t1.vt
de1_T1/simulation/modelsim/de1_t1.vt.bak
de1_T1/simulation/modelsim/de1_t1_modelsim.xrf
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak1
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak2
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak3
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak4
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak5
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak6
de1_T1/simulation/modelsim/de1_t1_run_msim_rtl_verilog.do.bak7
de1_T1/simulation/modelsim/de1_t1_run_ms

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