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文件名称:hw3

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    344.44kb
  • 已下载：
    0次
  • 提 供 者：
    vi***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.-Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down　otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting.　For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.
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下载文件列表

hw3\counter.asm.rpt
hw3\counter.done
hw3\counter.fit.rpt
hw3\counter.fit.smsg
hw3\counter.fit.summary
hw3\counter.flow.rpt
hw3\counter.map.rpt
hw3\counter.map.summary
hw3\counter.pin
hw3\counter.pof
hw3\counter.qpf
hw3\counter.qsf
hw3\counter.qws
hw3\counter.sim.rpt
hw3\counter.sof
hw3\counter.tan.rpt
hw3\counter.tan.summary
hw3\counter.vhd
hw3\counter.vwf
hw3\counter_assignment_defaults.qdf
hw3\db\counter.cbx.xml
hw3\db\counter.db_info
hw3\db\counter.eco.cdb
hw3\db\counter.eds_overflow
hw3\db\counter.fnsim.cdb
hw3\db\counter.fnsim.hdb
hw3\db\counter.fnsim.qmsg
hw3\db\counter.hier_info
hw3\db\counter.sim.hdb
hw3\db\counter.sim.qmsg
hw3\db\counter.sim.rdb
hw3\db\counter.simfam
hw3\db\counter.sim_ori.vwf
hw3\db\counter.sld_design_entry.sci
hw3\db\counter.sld_design_entry_dsc.sci
hw3\db\prev_cmp_counter.asm.qmsg
hw3\db\prev_cmp_counter.fit.qmsg
hw3\db\prev_cmp_counter.map.qmsg
hw3\db\prev_cmp_counter.qmsg
hw3\db\prev_cmp_counter.sim.qmsg
hw3\db\prev_cmp_counter.tan.qmsg
hw3\db\wed.wsf
hw3\incremental_db\compiled_partitions\counter.root_partition.cmp.atm
hw3\incremental_db\compiled_partitions\counter.root_partition.cmp.dfp
hw3\incremental_db\compiled_partitions\counter.root_partition.cmp.hdbx
hw3\incremental_db\compiled_partitions\counter.root_partition.cmp.kpt
hw3\incremental_db\compiled_partitions\counter.root_partition.cmp.logdb
hw3\incremental_db\compiled_partitions\counter.root_partition.cmp.rcf
hw3\incremental_db\compiled_partitions\counter.root_partition.map.atm
hw3\incremental_db\compiled_partitions\counter.root_partition.map.dpi
hw3\incremental_db\compiled_partitions\counter.root_partition.map.hdbx
hw3\incremental_db\compiled_partitions\counter.root_partition.map.kpt
hw3\incremental_db\README
hw3\printout\counter.pdf
hw3\printout\functional waveform 1.jpg
hw3\printout\functional waveform 2.jpg
hw3\printout\functional waveform 3.jpg

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