user_design/datasheet.txt
user_design/log.txt
user_design/mig.prj
user_design/par/create_ise.bat
user_design/par/icon_coregen.xco
user_design/par/ila_coregen.xco
user_design/par/ise_flow.bat
user_design/par/ise_run.txt
user_design/par/makeproj.bat
user_design/par/mem_interface_top.ut
user_design/par/readme.txt
user_design/par/rem_files.bat
user_design/par/set_ise_prop.tcl
user_design/par/spartan3A_DDR2_test_mig_v3_6.cdc
user_design/par/spartan3A_DDR2_test_mig_v3_6.ucf
user_design/par/vio_coregen.xco
user_design/rtl/spartan3A_DDR2_test_mig_v3_6.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_cal_ctl.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_cal_top.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_clk_dcm.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_controller_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_controller_iobs_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_data_path_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_data_path_iobs_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_data_read_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_data_read_controller_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_data_write_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_dqs_delay.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_fifo_0_wr_en_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_fifo_1_wr_en_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_infrastructure.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_infrastructure_iobs_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_infrastructure_top.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_iobs_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_parameters_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_ram8d_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_rd_gray_cntr.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_s3_dm_iob.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_s3_dqs_iob.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_s3_dq_iob.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_tap_dly.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_top_0.v
user_design/rtl/spartan3A_DDR2_test_mig_v3_6_wr_gray_cntr.v
user_design/sim/ddr2_model.v
user_design/sim/ddr2_model_parameters.vh
user_design/sim/sim.do
user_design/sim/sim_tb_top.v
user_design/sim/spartan3A_DDR2_test_mig_v3_6_addr_gen_0.v
user_design/sim/spartan3A_DDR2_test_mig_v3_6_cmd_fsm_0.v
user_design/sim/spartan3A_DDR2_test_mig_v3_6_cmp_data_0.v
user_design/sim/spartan3A_DDR2_test_mig_v3_6_data_gen_0.v
user_design/sim/spartan3A_DDR2_test_mig_v3_6_test_bench_0.v
user_design/sim/transcript
user_design/sim/vsim.wlf
user_design/sim/wiredly.v
user_design/sim/work/@wire@delay/verilog.asm
user_design/sim/work/@wire@delay/verilog.psm
user_design/sim/work/@wire@delay/verilog.rw
user_design/sim/work/@wire@delay/_primary.dat
user_design/sim/work/@wire@delay/_primary.dbs
user_design/sim/work/@wire@delay/_primary.vhd
user_design/sim/work/ddr2_model/verilog.asm
user_design/sim/work/ddr2_model/verilog.psm
user_design/sim/work/ddr2_model/verilog.rw
user_design/sim/work/ddr2_model/_primary.dat
user_design/sim/work/ddr2_model/_primary.dbs
user_design/sim/work/ddr2_model/_primary.vhd
user_design/sim/work/glbl/verilog.asm
user_design/sim/work/glbl/verilog.psm
user_design/sim/work/glbl/verilog.rw
user_design/sim/work/glbl/_primary.dat
user_design/sim/work/glbl/_primary.dbs
user_design/sim/work/glbl/_primary.vhd
user_design/sim/work/icon/verilog.asm
user_design/sim/work/icon/verilog.psm
user_design/sim/work/icon/verilog.rw
user_design/sim/work/icon/_primary.dat
user_design/sim/work/icon/_primary.dbs
user_design/sim/work/icon/_primary.vhd
user_design/sim/work/ila/verilog.asm
user_design/sim/work/ila/verilog.psm
user_design/sim/work/ila/verilog.rw
user_design/sim/work/ila/_primary.dat
user_design/sim/work/ila/_primary.dbs
user_design/sim/work/ila/_primary.vhd
user_design/sim/work/sim_tb_top/verilog.asm
user_design/sim/work/sim_tb_top/verilog.psm
user_design/sim/work/sim_tb_top/verilog.rw
user_design/sim/work/sim_tb_top/_primary.dat
user_design/sim/work/sim_tb_top/_primary.dbs
user_design/sim/work/sim_tb_top/_primary.vhd
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6/verilog.asm
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6/verilog.psm
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6/verilog.rw
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6/_primary.dat
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6/_primary.dbs
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6/_primary.vhd
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_addr_gen_0/verilog.asm
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_addr_gen_0/verilog.psm
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_addr_gen_0/verilog.rw
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_addr_gen_0/_primary.dat
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_addr_gen_0/_primary.dbs
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_addr_gen_0/_primary.vhd
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_cal_ctl/verilog.asm
user_design/sim/work/spartan3@a_@d@d@r2_test_mig_v3_6_cal_ctl/verilog.psm
user_design/sim/work/spartan3@