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文件名称:VHDL

  • 所属分类：
    Embeded-SCM Develop
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    468.97kb
  • 已下载：
    0次
  • 提 供 者：
    王***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于V6的pci-express 总线实现-Based on the pci-express bus V6 achieve
相关搜索： PIO_32_RX_ENGINE

(系统自动生成,下载前可以参看下载内容)

下载文件列表

VHDL/components.vhd
VHDL/designTop.vhd
VHDL/implementation.gise
VHDL/implementation.xise
VHDL/prebuilt_PCIe_SP605.ucf
VHDL/_xmsgs/pn_parser.xmsgs
VHDL/ipcore_dir/S6PCIeEP/s6_pcie_readme.txt
VHDL/ipcore_dir/S6PCIeEP/source/gtpa1_dual_wrapper.v
VHDL/ipcore_dir/S6PCIeEP/source/gtpa1_dual_wrapper.vhd
VHDL/ipcore_dir/S6PCIeEP/source/gtpa1_dual_wrapper_tile.v
VHDL/ipcore_dir/S6PCIeEP/source/gtpa1_dual_wrapper_tile.vhd
VHDL/ipcore_dir/S6PCIeEP/source/pcie_brams_s6.v
VHDL/ipcore_dir/S6PCIeEP/source/pcie_brams_s6.vhd
VHDL/ipcore_dir/S6PCIeEP/source/pcie_bram_s6.v
VHDL/ipcore_dir/S6PCIeEP/source/pcie_bram_s6.vhd
VHDL/ipcore_dir/S6PCIeEP/source/pcie_bram_top_s6.v
VHDL/ipcore_dir/S6PCIeEP/source/pcie_bram_top_s6.vhd
VHDL/ipcore_dir/S6PCIeEP/source/S6PCIeEP.v
VHDL/ipcore_dir/S6PCIeEP/source/S6PCIeEP.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/tests/tests.v
VHDL/ipcore_dir/S6PCIeEP/simulation/tests/tests.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/board.f
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/board.v
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/board.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/isim_cmd.tcl
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/simulate_isim.bat
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/simulate_isim.sh
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/simulate_mti.do
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/simulate_ncsim.sh
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/simulate_vcs.sh
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/sys_clk_gen.v
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/sys_clk_gen.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/sys_clk_gen_ds.v
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/sys_clk_gen_ds.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/wave.do
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/wave.sv
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/wave.tcl
VHDL/ipcore_dir/S6PCIeEP/simulation/functional/wave.wcfg
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_drp_chanalign_fix_3752_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_drp_chanalign_fix_3752_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_rx_valid_filter_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_rx_valid_filter_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_tx_sync_rate_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_tx_sync_rate_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_wrapper_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/gtx_wrapper_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_2_0_rport_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_2_0_rport_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_2_0_v6_rp.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_2_0_v6_rp.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_brams_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_brams_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_bram_top_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_bram_top_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_bram_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_bram_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_clocking_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_clocking_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_gtx_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_gtx_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_lane_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_lane_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_misc_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_misc_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_pipe_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_reset_delay_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_reset_delay_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_upconfig_fix_3451_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pcie_upconfig_fix_3451_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_cfg.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_cfg.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_com.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_pl.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_pl.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_rx.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_rx.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_tx.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/pci_exp_usrapp_tx.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/test_interface.vhd
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/xilinx_pcie_2_0_rport_v6.v
VHDL/ipcore_dir/S6PCIeEP/simulation/dsport/xilinx_pcie_2_0_rport_v6.vhd
VHDL/ipcore_dir/S6PCIeEP/implement/implement.bat
VHDL/ipcore_dir/S6PCIeEP/implement/implement.sh
VHDL/ipcore_dir/S6PCIeEP/implement/xst.prj
VHDL/ipcore_dir/S6PCIeEP/implement/xst.scr
VHDL/ipcore_dir/S6PCIeEP/example_design/pcie_app_s6.v
VHDL/ipcore_dir/S6PCIeEP/example_design/pcie_app_s6.vhd
VHDL/ipcore_dir/S6PCIeEP/example_design/PIO.v
VHDL/ipcore_dir/S6PCI

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