software/
software/cf_ideutils.c
software/cf_ideutils.h
software/cf_test.c
software/cf_testutils.c
software/ide.h
std_cf_1c20/
std_cf_1c20/.sopc_builder/
std_cf_1c20/.sopc_builder/install.ptf
std_cf_1c20/button_pio.v
std_cf_1c20/cf.v
std_cf_1c20/cmp_state.ini
std_cf_1c20/connector_pll.bsf
std_cf_1c20/connector_pll.v
std_cf_1c20/cpu.ocp
std_cf_1c20/cpu.v
std_cf_1c20/cpu_jtag_debug_module.v
std_cf_1c20/cpu_jtag_debug_module_wrapper.v
std_cf_1c20/cpu_mult_cell.v
std_cf_1c20/cpu_ociram_default_contents.mif
std_cf_1c20/cpu_test_bench.v
std_cf_1c20/db/
std_cf_1c20/db/standard.db_info
std_cf_1c20/db/standard.eco.cdb
std_cf_1c20/db/standard.sld_design_entry.sci
std_cf_1c20/delay_reset_block.bdf
std_cf_1c20/delay_reset_block.bsf
std_cf_1c20/epcs_controller.v
std_cf_1c20/epcs_controller_boot_rom.hex
std_cf_1c20/high_res_timer.v
std_cf_1c20/ic_tag_ram.mif
std_cf_1c20/jtag_uart.v
std_cf_1c20/led_pio.v
std_cf_1c20/reconfig_request_pio.v
std_cf_1c20/reset_counter.bsf
std_cf_1c20/reset_counter.v
std_cf_1c20/rf_ram_a.mif
std_cf_1c20/rf_ram_b.mif
std_cf_1c20/sdram.v
std_cf_1c20/sdram_pll.bsf
std_cf_1c20/sdram_pll.v
std_cf_1c20/sdram_pll_bb.v
std_cf_1c20/sdram_test_component.v
std_cf_1c20/seven_seg_pio.v
std_cf_1c20/sopc_builder_log.txt
std_cf_1c20/standard.bdf
std_cf_1c20/standard.qpf
std_cf_1c20/standard.qsf
std_cf_1c20/standard.qws
std_cf_1c20/standard.sof
std_cf_1c20/standard_assignment_defaults.qdf
std_cf_1c20/std_1c20.bsf
std_cf_1c20/std_1c20.ptf
std_cf_1c20/std_1c20.ptf.5.00
std_cf_1c20/std_1c20.v
std_cf_1c20/std_1c20_setup_quartus.tcl
std_cf_1c20/sysid.v
std_cf_1c20/sys_clk_timer.v
std_cf_1c20/uart1.v
std_cf_1s40/
std_cf_1s40/button_pio.v
std_cf_1s40/cf.v
std_cf_1s40/cpu.ocp
std_cf_1s40/cpu.v
std_cf_1s40/cpu_jtag_debug_module.v
std_cf_1s40/cpu_jtag_debug_module_wrapper.v
std_cf_1s40/cpu_mult_cell.v
std_cf_1s40/cpu_ociram_default_contents.mif
std_cf_1s40/cpu_test_bench.v
std_cf_1s40/db/
std_cf_1s40/db/standard.db_info
std_cf_1s40/db/standard.eco.cdb
std_cf_1s40/db/standard.sld_design_entry.sci
std_cf_1s40/delay_reset_block.bdf
std_cf_1s40/delay_reset_block.bsf
std_cf_1s40/high_res_timer.v
std_cf_1s40/ic_tag_ram.mif
std_cf_1s40/jtag_uart.v
std_cf_1s40/led_pio.v
std_cf_1s40/onchip_ram_64_kbytes.hex
std_cf_1s40/onchip_ram_64_kbytes.v
std_cf_1s40/reconfig_request_pio.v
std_cf_1s40/reset_counter.bsf
std_cf_1s40/reset_counter.v
std_cf_1s40/rf_ram_a.mif
std_cf_1s40/rf_ram_b.mif
std_cf_1s40/sdram.v
std_cf_1s40/sdram_pll.bsf
std_cf_1s40/sdram_pll.v
std_cf_1s40/sdram_pll_bb.v
std_cf_1s40/sdram_test_component.v
std_cf_1s40/seven_seg_pio.v
std_cf_1s40/sopc_builder_debug_log.txt
std_cf_1s40/standard.bdf
std_cf_1s40/standard.pin
std_cf_1s40/standard.qpf
std_cf_1s40/standard.qsf
std_cf_1s40/standard.qws
std_cf_1s40/standard_assignment_defaults.qdf
std_cf_1s40/std_1s40.bsf
std_cf_1s40/std_1s40.ptf
std_cf_1s40/std_1s40.v
std_cf_1s40/std_1s40_setup_quartus.tcl
std_cf_1s40/sysid.v
std_cf_1s40/sys_clk_timer.v
std_cf_1s40/uart1.v
std_cf_2c35/
std_cf_2c35/add_constraints_for_ddr_sdram.tcl
std_cf_2c35/auto_add_ddr_constraints.tcl
std_cf_2c35/auto_verify_ddr_timing.tcl
std_cf_2c35/bb_list.txt
std_cf_2c35/button_pio.v
std_cf_2c35/cf.v
std_cf_2c35/cmp_state.ini
std_cf_2c35/constraints_out.txt
std_cf_2c35/cpu.ocp
std_cf_2c35/cpu.v
std_cf_2c35/cpu_jtag_debug_module.v
std_cf_2c35/cpu_jtag_debug_module_wrapper.v
std_cf_2c35/cpu_mult_cell.v
std_cf_2c35/cpu_ociram_default_contents.mif
std_cf_2c35/cpu_test_bench.v
std_cf_2c35/ddr_lib_path.tcl
std_cf_2c35/ddr_pll_cycloneii.v
std_cf_2c35/ddr_sdram.cmp
std_cf_2c35/ddr_sdram.html
std_cf_2c35/ddr_sdram.inc
std_cf_2c35/ddr_sdram.v
std_cf_2c35/ddr_sdram_auk_ddr_clk_gen.v
std_cf_2c35/ddr_sdram_auk_ddr_datapath.v
std_cf_2c35/ddr_sdram_auk_ddr_dqs_group.v
std_cf_2c35/ddr_sdram_auk_ddr_sdram.v
std_cf_2c35/ddr_sdram_bb.v
std_cf_2c35/ddr_sdram_ddr_settings.txt
std_cf_2c35/ddr_sdram_debug_design.v
std_cf_2c35/ddr_sdram_debug_design_1.v
std_cf_2c35/ddr_sdram_debug_design_tb_1.v
std_cf_2c35/ddr_sdram_example_driver.v
std_cf_2c35/ddr_sdram_extraction_data.txt
std_cf_2c35/ddr_sdram_extraction_log.txt
std_cf_2c35/ddr_sdram_extraction_log2.txt
std_cf_2c35/ddr_sdram_inst.v
std_cf_2c35/ddr_sdram_post_summary.txt
std_cf_2c35/ddr_sdram_pre_compile_ddr_timing_summary.txt
std_cf_2c35/ddr_sdram_test_component.v
std_cf_2c35/epcs_controller.v
std_cf_2c35/epcs_controller_boot_rom.hex
std_cf_2c35/estimated_data.txt
std_cf_2c35/high_res_timer.v
std_cf_2c35/ic_tag_ram.mif
std_cf_2c35/jtag_uart.v
std_cf_2c35/led_pio.v
std_cf_2c35/pin_assignment_script.txt
std_cf_2c35/readme.txt
std_cf_2c35/reconfig_request_pio.v
std_cf_2c35/remove_add_constraints_for_ddr_sdram.tcl
std_cf_2c35/remove_add_constraints_for_ddr_sdram_2005_04_20___20_33.tcl
std_cf_2c35/remove_add_constraints_for_ddr_sdram_2005_05_13___11_42.tcl
std_cf_2c35/rf_ram_a.mif
std_cf_2c35/rf_ram_b.mif
std_cf_2c35/seven_seg_pio.v
std_cf_2c35/simgen_init.txt
std_cf_2c35/sopc_builder_debug_log.txt
std_cf_2c35/ssram_pll.v
std_cf_2c35/standard.bdf
std_cf_2c35/standard.pin
std_cf_2c35/standard.qpf
std_cf_2c35/standard.qsf
std_cf_2c35/standard.qws
std_cf_2c35/standard.sof
std_cf_2c35/std_2C35.bsf
std_cf_2