在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, the lower frequency clock signal. We know that the hardware circuit design clock signal is the most important one of the signals. Below us Divider VHDL descr iption of the source code for the completion of the clock signal CLK frequency of 2 hours, 4 frequency, frequency of 8 hours, 16 minutes frequency. This is the most simple-frequency circuit, only one counter will be.