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文件名称:histogram4

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    19.01mb
  • 已下载：
    0次
  • 提 供 者：
    杨****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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利用matlab和modelsim完成了用直方图均衡化处理灰色图片的前仿真，有处理前后图片的对比，verilog语言编写，但到用实时处理还差很远-Completed using matlab and modelsim deal with the gray image histogram equalization before the simulation, a comparison of before and after pictures, verilog language, but with real-time processing is very much far
相关搜索： histogram.v Verilog Histogram Equalization verilog histogram4.rar 直方图均衡化 histogram equalization using verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

histogram4/histogram2.v
histogram4/ram5.v
histogram4/Test_Top.v
histogram4/work/_info
histogram4/work/_temp/vlogbntzyn
histogram4/work/_temp/vlogqj22r4
histogram4/work/_temp/vlog8ey5i1
histogram4/work/_temp/vlogsifq0j
histogram4/work/_temp/vlogmrbdmx
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histogram4/work/_temp/vlogbtn3kg
histogram4/work/_temp/vlogc3cq8n
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histogram4/work/_temp/vlogny25tn
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histogram4/work/_temp/vloghew64k
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histogram4/work/_temp/vlogk8e61g
histogram4/work/_temp/vlog76wrb0
histogram4/work/_temp/vlog53tej0
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histogram4/work/_temp/vlogd85wd0
histogram4/work/_temp/vlogeyycfi
histogram4/work/_temp/vlogge1g66
histogram4/work/_temp/vlogdemb2d
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histogram4/work/_temp/vlog51w20d
histogram4/work/_temp/vlog44iqkn
histogram4/work/_temp/vlogy7c6r5
histogram4/work/_temp/vlogq8qcd4
histogram4/work/_temp/vlog2230gj
histogram4/work/_temp/vlogxin0jf
histogram4/work/_temp/vlog0q0mj8
histogram4/work/_temp/vlog94ez6b
histogram4/work/_temp/vlogdwae21
histogram4/work/_vmake
histogram4/work/@test_@top/_primary.vhd
histogram4/work/@test_@top/verilog.asm
histogram4/work/@test_@top/verilog.rw
histogram4/work/@test_@top/_primary.dbs
histogram4/work/@test_@top/_primary.dat
histogram4/work/histogram2/_primary.vhd
histogram4/work/histogram2/verilog.asm
histogram4/work/histogram2/verilog.rw
histogram4/work/histogram2/_primary.dbs
histogram4/work/histogram2/_primary.dat
histogram4/work/ram5/_primary.vhd
histogram4/work/ram5/verilog.asm
histogram4/work/ram5/verilog.rw
histogram4/work/ram5/_primary.dbs
histogram4/work/ram5/_primary.dat
histogram4/work/lcell/_primary.vhd
histogram4/work/lcell/verilog.asm
histogram4/work/lcell/verilog.rw
histogram4/work/lcell/_primary.dbs
histogram4/work/lcell/_primary.dat
histogram4/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
histogram4/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
histogram4/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.rw
histogram4/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dbs
histogram4/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
histogram4/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
histogram4/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
histogram4/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.rw
histogram4/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dbs
histogram4/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
histogram4/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
histogram4/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
histogram4/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.rw
histogram4/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs
histogram4/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
histogram4/work/dffp/_primary.vhd
histogram4/work/dffp/verilog.asm
histogram4/work/dffp/verilog.rw
histogram4/work/dffp/_primary.dbs
histogram4/work/dffp/_primary.dat
histogram4/work/pll_iobuf/_primary.vhd
histogram4/work/pll_iobuf/verilog.asm
histogram4/work/pll_iobuf/verilog.rw
histogram4/work/pll_iobuf/_primary.dbs
histogram4/work/pll_iobuf/_primary.dat
histogram4/work/stx_m_cntr/_primary.vhd
histogram4/work/stx_m_cntr/verilog.asm
histogram4/work/stx_m_cntr/verilog.rw
histogram4/work/stx_m_cntr/_primary.dbs
histogram4/work/stx_m_cntr/_primary.dat
histogram4/work/stx_n_cntr/_primary.vhd
histogram4/work/stx_n_cntr/verilog.asm
histogram4/work/stx_n_cntr/verilog.rw
histogram4/work/stx_n_cntr/_primary.dbs
histogram4/work/stx_n_cntr/_primary.dat
histogram4/work/stx_scale_cntr/_primary.vhd
histogram4/work/stx_scale_cntr/verilog.asm
histogram4/work/stx_scale_cntr/verilog.rw
histogram4/work/stx_scale_cntr/_primary.dbs
histogram4/work/stx_scale_cntr/_primary.dat
histogram4/work/@m@f_pll_reg/_primary.vhd
histogram4/work/@m@f_pll_reg/verilog.asm
histogram4/work/@m@f_pll_reg/verilog.rw
histogram4/work/@m@f_pll_reg/_primary.dbs
histogram4/work/@m@f_pll_reg/_primary.dat
histogram4/work/@m@f_stratix_pll/_primary.vhd
histogram4/work/@m@f_stratix_pll/verilog.asm
histogram4/work/@m@f_stratix_pll/verilog.rw
histogram4/work/@m@f_stratix_pll/_primary.dbs
histogram4/work/@m@f_stratix_pll/_primary.dat
histogram4/work/arm_m_cntr/_primary.vhd
histogram4/work/arm_m_cntr/verilog.asm
histogram4/work/arm_m_cntr/verilog.rw
histogram4/work/arm_m_cntr/_primary.dbs
histogram4/work/arm_m_cntr/_primary.dat
histogram4/work/arm_n_cntr/_primary.vhd
histogram4/work/arm_n_cntr/verilog.asm
histogram4/work/arm_n_cntr/verilog.rw
histogram4/work/arm_n_cntr/_primary.dbs
histogram4/work/arm_n_cntr/_primary.dat
histogram4/work/arm_scale_cntr/_primary.vhd
histogram4/work/arm_scale_cntr/verilog.asm
histogram4/work/arm_scale_cntr/verilog.rw
histogram4/work/arm_scale_cntr/_primary.dbs
histogram4/work/arm_scale_cntr/_primary.dat
histogram4/work/@m@f_stratixii_pll/_primary.vhd
histogram4/

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