文件名称:8bitcpu
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所属分类:
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- 上传时间:2012-11-16
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文件大小:4.52mb
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已下载:0次
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下载文件列表
final8/afterprcell.png
final8/afterprpower.png
final8/afterprtiming.png
final8/cell.rep
final8/code.hex
final8/command.log
final8/compile_bgx.scr
final8/compile_dc.scr
final8/cpu8.conn.rpt
final8/cpu8.cts_trace
final8/cpu8.db
final8/cpu8.geom.rpt
final8/cpu8.sdc
final8/cpu8.v
final8/cpu8.vh
final8/cpu8_test.v
final8/cts.rguide
final8/encounter.cmd
final8/encounter.cmd1
final8/encounter.conf
final8/encounter.cts
final8/encounter.io
final8/encounter.log
final8/encounter.log1
final8/encounter.tcl
final8/final.dspf
final8/final.gds2
final8/final.v
final8/gds2_encounter.map
final8/gds2_icfb.map
final8/gds2_seultra.map
final8/ipo1.txt
final8/ipo2.txt
final8/magic/AND2X1.ext
final8/magic/AND2X1.mag
final8/magic/AND2X2.ext
final8/magic/AND2X2.mag
final8/magic/AOI21X1.ext
final8/magic/AOI21X1.mag
final8/magic/AOI22X1.ext
final8/magic/AOI22X1.mag
final8/magic/BUFX2.ext
final8/magic/BUFX2.mag
final8/magic/BUFX4.mag
final8/magic/CLKBUF1.mag
final8/magic/CLKBUF2.mag
final8/magic/CLKBUF3.mag
final8/magic/cpu8.al
final8/magic/cpu8.ext
final8/magic/cpu8.mag
final8/magic/cpu8.nodes
final8/magic/cpu8.sim
final8/magic/cpu8_noRC.sim
final8/magic/cpu8_VIA0.ext
final8/magic/cpu8_VIA0.mag
final8/magic/cpu8_VIA1.ext
final8/magic/cpu8_VIA1.mag
final8/magic/DFFNEGX1.mag
final8/magic/DFFPOSX1.ext
final8/magic/DFFPOSX1.mag
final8/magic/DFFSR.mag
final8/magic/FAX1.mag
final8/magic/FILL.ext
final8/magic/FILL.mag
final8/magic/HAX1.mag
final8/magic/INVX1.mag
final8/magic/INVX2.ext
final8/magic/INVX2.mag
final8/magic/INVX4.ext
final8/magic/INVX4.mag
final8/magic/INVX8.ext
final8/magic/INVX8.mag
final8/magic/LATCH.mag
final8/magic/M2_M1.ext
final8/magic/M2_M1.mag
final8/magic/M3_M2.ext
final8/magic/M3_M2.mag
final8/magic/magic.log
final8/magic/MUX2X1.ext
final8/magic/MUX2X1.mag
final8/magic/NAND2X1.ext
final8/magic/NAND2X1.mag
final8/magic/NAND3X1.ext
final8/magic/NAND3X1.mag
final8/magic/NOR2X1.ext
final8/magic/NOR2X1.mag
final8/magic/NOR3X1.mag
final8/magic/OAI21X1.ext
final8/magic/OAI21X1.mag
final8/magic/OAI22X1.ext
final8/magic/OAI22X1.mag
final8/magic/OR2X1.mag
final8/magic/OR2X2.mag
final8/magic/osu_stdcells_pads.mag
final8/magic/PADFC.mag
final8/magic/PADGND.mag
final8/magic/PADINC.mag
final8/magic/PADINOUT.mag
final8/magic/PADNC.mag
final8/magic/PADOUT.mag
final8/magic/PADVDD.mag
final8/magic/TBUFX1.ext
final8/magic/TBUFX1.mag
final8/magic/TBUFX2.mag
final8/magic/XNOR2X1.ext
final8/magic/XNOR2X1.mag
final8/magic/XOR2X1.ext
final8/magic/XOR2X1.mag
final8/osu05_stdcells.v
final8/osu05_stdcells.vhdl
final8/pathmill.conf
final8/power.rep
final8/powrmill.conf
final8/primetime.scr
final8/readme.doc
final8/report.ctsmdl
final8/report.ctsrpt
final8/report.post_troute.ctsrpt
final8/seultra.scr
final8/shm.db/shm.dsn
final8/shm.db/shm.trn
final8/sim1.png
final8/sim2.png
final8/sim3.png
final8/skew.post_troute_local.ctsrpt
final8/stimulus32.v
final8/stim_proj.out
final8/sue/AND2X1.sue
final8/sue/AND2X2.sue
final8/sue/AOI21X1.sue
final8/sue/AOI22X1.sue
final8/sue/BUFX2.sue
final8/sue/BUFX4.sue
final8/sue/CLKBUF1.sue
final8/sue/CLKBUF2.sue
final8/sue/CLKBUF3.sue
final8/sue/cpu8.sim
final8/sue/cpu8.sue
final8/sue/cpu8.sue.BAK
final8/sue/DFFNEGX1.sue
final8/sue/DFFPOSX1.sue
final8/sue/DFFSR.sue
final8/sue/FAX1.sue
final8/sue/final.sim
final8/sue/final.v
final8/sue/HAX1.sue
final8/sue/INVX1.sue
final8/sue/INVX2.sue
final8/sue/INVX4.sue
final8/sue/INVX8.sue
final8/sue/LATCH.sue
final8/sue/MUX2X1.sue
final8/sue/NAND2X1.sue
final8/sue/NAND3X1.sue
final8/sue/NOR2X1.sue
final8/sue/NOR3X1.sue
final8/sue/OAI21X1.sue
final8/sue/OAI22X1.sue
final8/sue/OR2X1.sue
final8/sue/OR2X2.sue
final8/sue/PADGND.sue
final8/sue/PADINC.sue
final8/sue/PADINOUT.sue
final8/sue/PADOUT.sue
final8/sue/PADVDD.sue
final8/sue/TBUFX1.sue
final8/sue/TBUFX2.sue
final8/sue/tclIndex
final8/sue/XNOR2X1.sue
final8/sue/XOR2X1.sue
final8/timing.rep
final8/timing.rep.1.placed
final8/timing.rep.2.ipo1
final8/timing.rep.3.cts
final8/timing.rep.4.ipo2
final8/timing.rep.5.final
final8/verilog.log
final8/WORK/adder-verilog.pvl
final8/WORK/ADDER.mr
final8/WORK/adder_8-verilog.pvl
final8/WORK/ADDER_8.mr
final8/WORK/addsub_8-verilog.pvl
final8/WORK/ADDSUB_8.mr
final8/WORK/alu_8-verilog.pvl
final8/WORK/ALU_8.mr
final8/WORK/and_8-verilog.pvl
final8/WORK/AND_8.mr
final8/WORK/control-verilog.pvl
final8/WORK/CONTROL.mr
final8/WORK/cpu8-verilog.pvl
final8/WORK/CPU8.mr
final8/WORK/decoder2to4-verilog.pvl
final8/WORK/DECODER2TO4.mr
final8/WORK/decoder3to8-verilog.pvl
final8/WORK/DECODER3TO8.mr
final8/WORK/decoder4to16-verilog.pvl
final8/WORK/DECODER4TO16.mr
final8/WORK/dff-verilog.pvl
final8/WORK/DFF.mr
final8/WORK/dff_8-verilog.pvl
final8/WORK/DFF_8.mr
final8/WORK/inc_8-verilog.pvl
final8/WORK/INC_8.mr
final8/WORK/memory16_8-verilog.pvl
final8/WORK/MEMORY16_8.mr
final8/WORK/memory_8-verilog.pvl
final8/WORK/MEMORY_8.mr
final8/WORK/mux2to1-verilog.pvl
final8/WORK/MUX2TO1.mr
final8/WORK/mux2to1_8-verilog.pvl
final8/WORK/MUX2TO1_8.mr
final8/WORK/PC-verilog.pvl
final8/WORK/PC.mr
final8/WORK/shift_left_logic_8-verilog.pvl
final8/WORK/SHIFT_LEFT_LOGIC_8.mr
final8/WORK/shift_right_logic_8-verilog.pvl
final8/WORK/SHIFT_RIGHT_LOGIC_
final8/afterprpower.png
final8/afterprtiming.png
final8/cell.rep
final8/code.hex
final8/command.log
final8/compile_bgx.scr
final8/compile_dc.scr
final8/cpu8.conn.rpt
final8/cpu8.cts_trace
final8/cpu8.db
final8/cpu8.geom.rpt
final8/cpu8.sdc
final8/cpu8.v
final8/cpu8.vh
final8/cpu8_test.v
final8/cts.rguide
final8/encounter.cmd
final8/encounter.cmd1
final8/encounter.conf
final8/encounter.cts
final8/encounter.io
final8/encounter.log
final8/encounter.log1
final8/encounter.tcl
final8/final.dspf
final8/final.gds2
final8/final.v
final8/gds2_encounter.map
final8/gds2_icfb.map
final8/gds2_seultra.map
final8/ipo1.txt
final8/ipo2.txt
final8/magic/AND2X1.ext
final8/magic/AND2X1.mag
final8/magic/AND2X2.ext
final8/magic/AND2X2.mag
final8/magic/AOI21X1.ext
final8/magic/AOI21X1.mag
final8/magic/AOI22X1.ext
final8/magic/AOI22X1.mag
final8/magic/BUFX2.ext
final8/magic/BUFX2.mag
final8/magic/BUFX4.mag
final8/magic/CLKBUF1.mag
final8/magic/CLKBUF2.mag
final8/magic/CLKBUF3.mag
final8/magic/cpu8.al
final8/magic/cpu8.ext
final8/magic/cpu8.mag
final8/magic/cpu8.nodes
final8/magic/cpu8.sim
final8/magic/cpu8_noRC.sim
final8/magic/cpu8_VIA0.ext
final8/magic/cpu8_VIA0.mag
final8/magic/cpu8_VIA1.ext
final8/magic/cpu8_VIA1.mag
final8/magic/DFFNEGX1.mag
final8/magic/DFFPOSX1.ext
final8/magic/DFFPOSX1.mag
final8/magic/DFFSR.mag
final8/magic/FAX1.mag
final8/magic/FILL.ext
final8/magic/FILL.mag
final8/magic/HAX1.mag
final8/magic/INVX1.mag
final8/magic/INVX2.ext
final8/magic/INVX2.mag
final8/magic/INVX4.ext
final8/magic/INVX4.mag
final8/magic/INVX8.ext
final8/magic/INVX8.mag
final8/magic/LATCH.mag
final8/magic/M2_M1.ext
final8/magic/M2_M1.mag
final8/magic/M3_M2.ext
final8/magic/M3_M2.mag
final8/magic/magic.log
final8/magic/MUX2X1.ext
final8/magic/MUX2X1.mag
final8/magic/NAND2X1.ext
final8/magic/NAND2X1.mag
final8/magic/NAND3X1.ext
final8/magic/NAND3X1.mag
final8/magic/NOR2X1.ext
final8/magic/NOR2X1.mag
final8/magic/NOR3X1.mag
final8/magic/OAI21X1.ext
final8/magic/OAI21X1.mag
final8/magic/OAI22X1.ext
final8/magic/OAI22X1.mag
final8/magic/OR2X1.mag
final8/magic/OR2X2.mag
final8/magic/osu_stdcells_pads.mag
final8/magic/PADFC.mag
final8/magic/PADGND.mag
final8/magic/PADINC.mag
final8/magic/PADINOUT.mag
final8/magic/PADNC.mag
final8/magic/PADOUT.mag
final8/magic/PADVDD.mag
final8/magic/TBUFX1.ext
final8/magic/TBUFX1.mag
final8/magic/TBUFX2.mag
final8/magic/XNOR2X1.ext
final8/magic/XNOR2X1.mag
final8/magic/XOR2X1.ext
final8/magic/XOR2X1.mag
final8/osu05_stdcells.v
final8/osu05_stdcells.vhdl
final8/pathmill.conf
final8/power.rep
final8/powrmill.conf
final8/primetime.scr
final8/readme.doc
final8/report.ctsmdl
final8/report.ctsrpt
final8/report.post_troute.ctsrpt
final8/seultra.scr
final8/shm.db/shm.dsn
final8/shm.db/shm.trn
final8/sim1.png
final8/sim2.png
final8/sim3.png
final8/skew.post_troute_local.ctsrpt
final8/stimulus32.v
final8/stim_proj.out
final8/sue/AND2X1.sue
final8/sue/AND2X2.sue
final8/sue/AOI21X1.sue
final8/sue/AOI22X1.sue
final8/sue/BUFX2.sue
final8/sue/BUFX4.sue
final8/sue/CLKBUF1.sue
final8/sue/CLKBUF2.sue
final8/sue/CLKBUF3.sue
final8/sue/cpu8.sim
final8/sue/cpu8.sue
final8/sue/cpu8.sue.BAK
final8/sue/DFFNEGX1.sue
final8/sue/DFFPOSX1.sue
final8/sue/DFFSR.sue
final8/sue/FAX1.sue
final8/sue/final.sim
final8/sue/final.v
final8/sue/HAX1.sue
final8/sue/INVX1.sue
final8/sue/INVX2.sue
final8/sue/INVX4.sue
final8/sue/INVX8.sue
final8/sue/LATCH.sue
final8/sue/MUX2X1.sue
final8/sue/NAND2X1.sue
final8/sue/NAND3X1.sue
final8/sue/NOR2X1.sue
final8/sue/NOR3X1.sue
final8/sue/OAI21X1.sue
final8/sue/OAI22X1.sue
final8/sue/OR2X1.sue
final8/sue/OR2X2.sue
final8/sue/PADGND.sue
final8/sue/PADINC.sue
final8/sue/PADINOUT.sue
final8/sue/PADOUT.sue
final8/sue/PADVDD.sue
final8/sue/TBUFX1.sue
final8/sue/TBUFX2.sue
final8/sue/tclIndex
final8/sue/XNOR2X1.sue
final8/sue/XOR2X1.sue
final8/timing.rep
final8/timing.rep.1.placed
final8/timing.rep.2.ipo1
final8/timing.rep.3.cts
final8/timing.rep.4.ipo2
final8/timing.rep.5.final
final8/verilog.log
final8/WORK/adder-verilog.pvl
final8/WORK/ADDER.mr
final8/WORK/adder_8-verilog.pvl
final8/WORK/ADDER_8.mr
final8/WORK/addsub_8-verilog.pvl
final8/WORK/ADDSUB_8.mr
final8/WORK/alu_8-verilog.pvl
final8/WORK/ALU_8.mr
final8/WORK/and_8-verilog.pvl
final8/WORK/AND_8.mr
final8/WORK/control-verilog.pvl
final8/WORK/CONTROL.mr
final8/WORK/cpu8-verilog.pvl
final8/WORK/CPU8.mr
final8/WORK/decoder2to4-verilog.pvl
final8/WORK/DECODER2TO4.mr
final8/WORK/decoder3to8-verilog.pvl
final8/WORK/DECODER3TO8.mr
final8/WORK/decoder4to16-verilog.pvl
final8/WORK/DECODER4TO16.mr
final8/WORK/dff-verilog.pvl
final8/WORK/DFF.mr
final8/WORK/dff_8-verilog.pvl
final8/WORK/DFF_8.mr
final8/WORK/inc_8-verilog.pvl
final8/WORK/INC_8.mr
final8/WORK/memory16_8-verilog.pvl
final8/WORK/MEMORY16_8.mr
final8/WORK/memory_8-verilog.pvl
final8/WORK/MEMORY_8.mr
final8/WORK/mux2to1-verilog.pvl
final8/WORK/MUX2TO1.mr
final8/WORK/mux2to1_8-verilog.pvl
final8/WORK/MUX2TO1_8.mr
final8/WORK/PC-verilog.pvl
final8/WORK/PC.mr
final8/WORK/shift_left_logic_8-verilog.pvl
final8/WORK/SHIFT_LEFT_LOGIC_8.mr
final8/WORK/shift_right_logic_8-verilog.pvl
final8/WORK/SHIFT_RIGHT_LOGIC_
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