文件名称:DDR1_2_WITHOUTDQ
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- 上传时间:2012-11-16
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文件大小:7.63mb
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已下载:0次
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DDR1 memory code in vhdl
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下载文件列表
DDR1_2_WITHOUTDQ/ddr.v
DDR1_2_WITHOUTDQ/DDR1_2.gise
DDR1_2_WITHOUTDQ/DDR1_2.ise
DDR1_2_WITHOUTDQ/DDR1_2.ise_ISE_Backup
DDR1_2_WITHOUTDQ/DDR1_2.ntrc_log
DDR1_2_WITHOUTDQ/DDR1_2.restore
DDR1_2_WITHOUTDQ/DDR1_2.xise
DDR1_2_WITHOUTDQ/DDR1_2_ise11migration.zip
DDR1_2_WITHOUTDQ/DDR1_2_xdb/cst.xbcd
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/version
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/common/HierarchicalDesign/HDProject
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/common/HierarchicalDesign/HDProject_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/common/__stored_object_table__
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Colors
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Colors_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Groups
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Groups_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VERILOG
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VERILOG_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-PostTransSim-
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-BehavioralSim-AutoCompile
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-DDR1_top
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-Factory-Default
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-mem_interface_top
DDR1_2_WITHOUTDQ/DD
DDR1_2_WITHOUTDQ/DDR1_2.gise
DDR1_2_WITHOUTDQ/DDR1_2.ise
DDR1_2_WITHOUTDQ/DDR1_2.ise_ISE_Backup
DDR1_2_WITHOUTDQ/DDR1_2.ntrc_log
DDR1_2_WITHOUTDQ/DDR1_2.restore
DDR1_2_WITHOUTDQ/DDR1_2.xise
DDR1_2_WITHOUTDQ/DDR1_2_ise11migration.zip
DDR1_2_WITHOUTDQ/DDR1_2_xdb/cst.xbcd
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/version
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/common/HierarchicalDesign/HDProject
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/common/HierarchicalDesign/HDProject_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/common/__stored_object_table__
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Colors
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Colors_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Groups
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ExpandedNetlistEngine/Groups_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VERILOG
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VERILOG_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-BehavioralSim-_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-PostTransSim-
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VERILOG
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VERILOG_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-BehavioralSim-AutoCompile
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-PostTransSim-AutoCompile
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-SynthesisOnly-AutoCompile
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module_StrTbl
DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-DDR1_top
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DDR1_2_WITHOUTDQ/DDR1_2_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-mem_interface_top
DDR1_2_WITHOUTDQ/DD
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