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文件名称:zxcpu

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Text]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.03mb
  • 已下载：
    0次
  • 提 供 者：
    zha****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
相关搜索： 16 bit risc cpu 16 bit RISC processor Design

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下载文件列表

zxcpu/.untf
zxcpu/automake.log
zxcpu/back.ANT
zxcpu/back.fdo
zxcpu/back.tbw
zxcpu/back.udo
zxcpu/back.vhw
zxcpu/backwr.cmd_log
zxcpu/backwr.lso
zxcpu/backwr.ngc
zxcpu/backwr.ngr
zxcpu/backwr.prj
zxcpu/backwr.stx
zxcpu/backwr.syr
zxcpu/backwr.vhdl
zxcpu/bitgen.ut
zxcpu/clk.ANT
zxcpu/clk.fdo
zxcpu/clk.tbw
zxcpu/clk.udo
zxcpu/clk.vhw
zxcpu/clock.cmd_log
zxcpu/clock.lso
zxcpu/clock.ngc
zxcpu/clock.ngr
zxcpu/clock.prj
zxcpu/clock.stx
zxcpu/clock.syr
zxcpu/clock.vhdl
zxcpu/coregen.log
zxcpu/coregen.prj
zxcpu/coregen_lock
zxcpu/CPU
zxcpu/cpu.bgn
zxcpu/cpu.bit
zxcpu/cpu.bld
zxcpu/cpu.cmd_log
zxcpu/cpu.dhp
zxcpu/cpu.drc
zxcpu/cpu.lso
zxcpu/cpu.mrp
zxcpu/cpu.nc1
zxcpu/cpu.ncd
zxcpu/cpu.ngc
zxcpu/cpu.ngd
zxcpu/cpu.ngm
zxcpu/cpu.ngr
zxcpu/cpu.npl
zxcpu/cpu.pad
zxcpu/cpu.pad_txt
zxcpu/cpu.par
zxcpu/cpu.pcf
zxcpu/cpu.placed_ncd_tracker
zxcpu/cpu.prj
zxcpu/cpu.routed_ncd_tracker
zxcpu/cpu.stx
zxcpu/cpu.syr
zxcpu/cpu.twr
zxcpu/cpu.twx
zxcpu/cpu.ucf
zxcpu/cpu.ucf.untf
zxcpu/cpu.ut
zxcpu/cpu.vhdl
zxcpu/cpu.xpi
zxcpu/cpuall.vhdl
zxcpu/CPUdata
zxcpu/cpuw.ANT
zxcpu/cpuw.fdo
zxcpu/cpuw.tbw
zxcpu/cpuw.udo
zxcpu/cpuw.vhw
zxcpu/cpu_last_par.ncd
zxcpu/cpu_map.ncd
zxcpu/cpu_map.ngm
zxcpu/cpu_pad.csv
zxcpu/cpu_pad.txt
zxcpu/fet.ANT
zxcpu/fet.fdo
zxcpu/fet.tbw
zxcpu/fet.udo
zxcpu/fet.vhw
zxcpu/fetch.cmd_log
zxcpu/fetch.lso
zxcpu/fetch.ngc
zxcpu/fetch.ngr
zxcpu/fetch.prj
zxcpu/fetch.stx
zxcpu/fetch.syr
zxcpu/fetch.vhdl
zxcpu/mem.ANT
zxcpu/mem.fdo
zxcpu/mem.tbw
zxcpu/mem.udo
zxcpu/mem.vhw
zxcpu/memory.cmd_log
zxcpu/memory.lso
zxcpu/memory.ngc
zxcpu/memory.ngr
zxcpu/memory.prj
zxcpu/memory.stx
zxcpu/memory.syr
zxcpu/memory.vhdl
zxcpu/op.tbw
zxcpu/oper.cmd_log
zxcpu/oper.lso
zxcpu/oper.ngc
zxcpu/oper.ngr
zxcpu/oper.prj
zxcpu/oper.stx
zxcpu/oper.syr
zxcpu/oper.vhdl
zxcpu/pepExtractor.prj
zxcpu/results.txt
zxcpu/transcript
zxcpu/vsim.wlf
zxcpu/work/back/testbench_arch.dat
zxcpu/work/back/testbench_arch.psm
zxcpu/work/back/_primary.dat
zxcpu/work/backwr/behavioral.dat
zxcpu/work/backwr/behavioral.psm
zxcpu/work/backwr/_primary.dat
zxcpu/work/backwr_cfg/_primary.dat
zxcpu/work/backwr_cfg/_vhdl.psm
zxcpu/work/clk/testbench_arch.dat
zxcpu/work/clk/testbench_arch.psm
zxcpu/work/clk/_primary.dat
zxcpu/work/clock/behavioral.dat
zxcpu/work/clock/behavioral.psm
zxcpu/work/clock/_primary.dat
zxcpu/work/clock_cfg/_primary.dat
zxcpu/work/clock_cfg/_vhdl.psm
zxcpu/work/cpu/behavioral.dat
zxcpu/work/cpu/behavioral.psm
zxcpu/work/cpu/_primary.dat
zxcpu/work/cpuw/testbench_arch.dat
zxcpu/work/cpuw/testbench_arch.psm
zxcpu/work/cpuw/_primary.dat
zxcpu/work/cpu_cfg/_primary.dat
zxcpu/work/cpu_cfg/_vhdl.psm
zxcpu/work/fet/testbench_arch.dat
zxcpu/work/fet/testbench_arch.psm
zxcpu/work/fet/_primary.dat
zxcpu/work/fetch/behavioral.dat
zxcpu/work/fetch/behavioral.psm
zxcpu/work/fetch/_primary.dat
zxcpu/work/fetch_cfg/_primary.dat
zxcpu/work/fetch_cfg/_vhdl.psm
zxcpu/work/mem/testbench_arch.dat
zxcpu/work/mem/testbench_arch.psm
zxcpu/work/mem/_primary.dat
zxcpu/work/memory/behavioral.dat
zxcpu/work/memory/behavioral.psm
zxcpu/work/memory/_primary.dat
zxcpu/work/memory_cfg/_primary.dat
zxcpu/work/memory_cfg/_vhdl.psm
zxcpu/work/oper/behavioral.dat
zxcpu/work/oper/behavioral.psm
zxcpu/work/oper/_primary.dat
zxcpu/work/_info
zxcpu/xst/work/hdllib.ref
zxcpu/xst/work/hdpdeps.ref
zxcpu/xst/work/sub00/vhpl00.vho
zxcpu/xst/work/sub00/vhpl01.vho
zxcpu/xst/work/sub00/vhpl02.vho
zxcpu/xst/work/sub00/vhpl03.vho
zxcpu/xst/work/sub00/vhpl04.vho
zxcpu/xst/work/sub00/vhpl05.vho
zxcpu/xst/work/sub00/vhpl06.vho
zxcpu/xst/work/sub00/vhpl07.vho
zxcpu/xst/work/sub00/vhpl08.vho
zxcpu/xst/work/sub00/vhpl09.vho
zxcpu/xst/work/sub00/vhpl10.vho
zxcpu/xst/work/sub00/vhpl11.vho
zxcpu/_ngo/netlist.lst
zxcpu/__projnav/backwr.xst
zxcpu/__projnav/bitgen.rsp
zxcpu/__projnav/clock.xst
zxcpu/__projnav/coregen.rsp
zxcpu/__projnav/cpu.gfl
zxcpu/__projnav/cpu.xst
zxcpu/__projnav/cpu_flowplus.gfl
zxcpu/__projnav/cpu_ncdTOut_tcl.rsp
zxcpu/__projnav/ednTOngd_tcl.rsp
zxcpu/__projnav/fetch.xst
zxcpu/__projnav/hb_cmds
zxcpu/__projnav/map.log
zxcpu/__projnav/memory.xst
zxcpu/__projnav/nc1TOncd_tcl.rsp
zxcpu/__projnav/oper.xst
zxcpu/__projnav/par.log
zxcpu/__projnav/parentEditConstraintsTextApp_tcl.rsp
zxcpu/__projnav/posttrc.log
zxcpu/__projnav/runXst_tcl.rsp
zxcpu/__projnav.log
zxcpu/xst/work/sub00
zxcpu/work/back
zxcpu/work/backwr
zxcpu/work/backwr_cfg
zxcpu/work/clk
zxcpu/work/clock
zxcpu/work/clock_cfg
zxcpu/work/cpu
zxcpu/work/cpuw
zxcpu/work/cpu_cfg
zxcpu/work/fet
zxcpu/work/fetch
zxcpu/work/fetch_cfg
zxcpu/work/mem
zxcpu/work/memory
zxcpu/work/memory_cfg
zxcpu/work/oper
zxcpu/xst/work
zxcpu/work
zxcpu/xst
zxcpu/_ngo
zxcpu/__projnav
zxcpu

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