文件名称:LAB17
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- 上传时间:2012-11-16
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学校FPGA实验教学work1之十七讲,西欧啊次哦十六讲-Schools Experiment work1 the seventh FPGA say, oh sixteen times in Western Europe say ah
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下载文件列表
LAB17/db/design.(0).cnf.cdb
LAB17/db/design.(0).cnf.hdb
LAB17/db/design.(1).cnf.cdb
LAB17/db/design.(1).cnf.hdb
LAB17/db/design.asm.qmsg
LAB17/db/design.asm_labs.ddb
LAB17/db/design.cbx.xml
LAB17/db/design.cmp.cdb
LAB17/db/design.cmp.hdb
LAB17/db/design.cmp.logdb
LAB17/db/design.cmp.rdb
LAB17/db/design.cmp.tdb
LAB17/db/design.cmp0.ddb
LAB17/db/design.cmp2.ddb
LAB17/db/design.db_info
LAB17/db/design.eco.cdb
LAB17/db/design.fit.qmsg
LAB17/db/design.hier_info
LAB17/db/design.hif
LAB17/db/design.map.cdb
LAB17/db/design.map.hdb
LAB17/db/design.map.logdb
LAB17/db/design.map.qmsg
LAB17/db/design.pre_map.cdb
LAB17/db/design.pre_map.hdb
LAB17/db/design.rtlv.hdb
LAB17/db/design.rtlv_sg.cdb
LAB17/db/design.rtlv_sg_swap.cdb
LAB17/db/design.sgdiff.cdb
LAB17/db/design.sgdiff.hdb
LAB17/db/design.signalprobe.cdb
LAB17/db/design.sim.vwf
LAB17/db/design.sld_design_entry.sci
LAB17/db/design.sld_design_entry_dsc.sci
LAB17/db/design.syn_hier_info
LAB17/db/design.tan.qmsg
LAB17/db/design.tis_db_list.ddb
LAB17/db/design.tmw_info
LAB17/db/wed.zsf
LAB17/design.asm.rpt
LAB17/design.bdf
LAB17/design.cdf
LAB17/design.done
LAB17/design.dpf
LAB17/design.fit.rpt
LAB17/design.fit.smsg
LAB17/design.fit.summary
LAB17/design.flow.rpt
LAB17/design.map.rpt
LAB17/design.map.summary
LAB17/design.pin
LAB17/design.pof
LAB17/design.qpf
LAB17/design.qsf
LAB17/design.qws
LAB17/design.sim.rpt
LAB17/design.sof
LAB17/design.tan.rpt
LAB17/design.tan.summary
LAB17/design.vwf
LAB17/design_assignment_defaults.qdf
LAB17/voter7.bsf
LAB17/voter7.v
LAB17/db
LAB17
LAB17/db/design.(0).cnf.hdb
LAB17/db/design.(1).cnf.cdb
LAB17/db/design.(1).cnf.hdb
LAB17/db/design.asm.qmsg
LAB17/db/design.asm_labs.ddb
LAB17/db/design.cbx.xml
LAB17/db/design.cmp.cdb
LAB17/db/design.cmp.hdb
LAB17/db/design.cmp.logdb
LAB17/db/design.cmp.rdb
LAB17/db/design.cmp.tdb
LAB17/db/design.cmp0.ddb
LAB17/db/design.cmp2.ddb
LAB17/db/design.db_info
LAB17/db/design.eco.cdb
LAB17/db/design.fit.qmsg
LAB17/db/design.hier_info
LAB17/db/design.hif
LAB17/db/design.map.cdb
LAB17/db/design.map.hdb
LAB17/db/design.map.logdb
LAB17/db/design.map.qmsg
LAB17/db/design.pre_map.cdb
LAB17/db/design.pre_map.hdb
LAB17/db/design.rtlv.hdb
LAB17/db/design.rtlv_sg.cdb
LAB17/db/design.rtlv_sg_swap.cdb
LAB17/db/design.sgdiff.cdb
LAB17/db/design.sgdiff.hdb
LAB17/db/design.signalprobe.cdb
LAB17/db/design.sim.vwf
LAB17/db/design.sld_design_entry.sci
LAB17/db/design.sld_design_entry_dsc.sci
LAB17/db/design.syn_hier_info
LAB17/db/design.tan.qmsg
LAB17/db/design.tis_db_list.ddb
LAB17/db/design.tmw_info
LAB17/db/wed.zsf
LAB17/design.asm.rpt
LAB17/design.bdf
LAB17/design.cdf
LAB17/design.done
LAB17/design.dpf
LAB17/design.fit.rpt
LAB17/design.fit.smsg
LAB17/design.fit.summary
LAB17/design.flow.rpt
LAB17/design.map.rpt
LAB17/design.map.summary
LAB17/design.pin
LAB17/design.pof
LAB17/design.qpf
LAB17/design.qsf
LAB17/design.qws
LAB17/design.sim.rpt
LAB17/design.sof
LAB17/design.tan.rpt
LAB17/design.tan.summary
LAB17/design.vwf
LAB17/design_assignment_defaults.qdf
LAB17/voter7.bsf
LAB17/voter7.v
LAB17/db
LAB17
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