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文件名称:stratix_pci_kit-v1.0

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    3.69mb
  • 已下载：
    0次
  • 提 供 者：
    sha***
  • 相关连接：
    无
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altera PCI总线接口参考设计源代码。使用PCI编译器中的mt64兆核函数实现PCI总线接口-altera PCI bus interface reference design source code. Using the PCI Compiler mt64 trillion nuclear functions for PCI bus interface
相关搜索： altera stratix PCI ALTERA PCI PCI_MT64 pudn pci

(系统自动生成,下载前可以参看下载内容)

下载文件列表

stratix_pci_kit-v1.0.0/bin/
stratix_pci_kit-v1.0.0/bin/altera.inf
stratix_pci_kit-v1.0.0/bin/megaicon.ico
stratix_pci_kit-v1.0.0/bin/StratixPCI.exe
stratix_pci_kit-v1.0.0/bin/STRATIX_KIT_APP_HELP.GID
stratix_pci_kit-v1.0.0/bin/STRATIX_KIT_APP_HELP.HLP
stratix_pci_kit-v1.0.0/bin/wdreg.exe
stratix_pci_kit-v1.0.0/bin/windrvr6.inf
stratix_pci_kit-v1.0.0/bin/windrvr6.sys
stratix_pci_kit-v1.0.0/constraints/
stratix_pci_kit-v1.0.0/constraints/mt32_23_ep1s25f1020c5_66_03_04.tcl
stratix_pci_kit-v1.0.0/constraints/mt64_23_ep1s25f1020c5_66_03_04.tcl
stratix_pci_kit-v1.0.0/constraints/Stratix_PCI_Board_DDR_settings.tcl
stratix_pci_kit-v1.0.0/constraints/t32_23_ep1s25f1020c5_66_03_04.tcl
stratix_pci_kit-v1.0.0/doc/
stratix_pci_kit-v1.0.0/doc/an223.pdf
stratix_pci_kit-v1.0.0/doc/banner.jpg
stratix_pci_kit-v1.0.0/doc/ds_StratixPciBd.pdf
stratix_pci_kit-v1.0.0/doc/readmeStratixPciKit.htm
stratix_pci_kit-v1.0.0/doc/StratixPciKitDocContents.pdf
stratix_pci_kit-v1.0.0/doc/ug_StratixPciKit.pdf
stratix_pci_kit-v1.0.0/max_config/
stratix_pci_kit-v1.0.0/max_config/max_stratix_config.pof
stratix_pci_kit-v1.0.0/reference_design/
stratix_pci_kit-v1.0.0/reference_design/sim/
stratix_pci_kit-v1.0.0/reference_design/sim/modelsim.ini
stratix_pci_kit-v1.0.0/reference_design/sim/sim.do
stratix_pci_kit-v1.0.0/reference_design/sim/stratix_pci2ddr.mpf
stratix_pci_kit-v1.0.0/reference_design/sim/stratix_pci2ddr_tb.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/trgt_tranx_mem_init.dat
stratix_pci_kit-v1.0.0/reference_design/sim/wave_stratix_pciddr.do
stratix_pci_kit-v1.0.0/reference_design/sim/altera_lib/
stratix_pci_kit-v1.0.0/reference_design/sim/altera_lib/altera_mf.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/ddr_dimm/
stratix_pci_kit-v1.0.0/reference_design/sim/ddr_dimm/ddr_dimm_model.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/ddr_dimm/mt46v32m8.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/arbiter.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/clk_gen.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/log.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/monitor.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/mstr_pkg.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/mstr_tranx.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/pull_up.vhd
stratix_pci_kit-v1.0.0/reference_design/sim/pci_bfm/trgt_tranx.vhd
stratix_pci_kit-v1.0.0/reference_design/syn_1s25/
stratix_pci_kit-v1.0.0/reference_design/syn_1s25/stratix_top.csf
stratix_pci_kit-v1.0.0/reference_design/syn_1s25/stratix_top.esf
stratix_pci_kit-v1.0.0/reference_design/syn_1s25/stratix_top.psf
stratix_pci_kit-v1.0.0/reference_design/syn_1s25/stratix_top.quartus
stratix_pci_kit-v1.0.0/reference_design/syn_1s25/stratix_top.rbf
stratix_pci_kit-v1.0.0/reference_design/syn_1s25/stratix_top.sof
stratix_pci_kit-v1.0.0/reference_design/vhdl/
stratix_pci_kit-v1.0.0/reference_design/vhdl/stratix_enh_pll.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/stratix_top.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/vhdl_components.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_cntrl/
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_cntrl/ddr_top.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/adr_gen.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/clk_sync.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/cntrl_intf.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/ddr_intf.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/mr_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/mw_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/tr_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/ddr_intf/tw_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/flash_cntrl/
stratix_pci_kit-v1.0.0/reference_design/vhdl/flash_cntrl/erase_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/flash_cntrl/flash_mem_cntrl.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/flash_cntrl/read_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/flash_cntrl/write_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/backend.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/cnten.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/datapath_fifo.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/dma.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/dma_reg.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/dma_sm.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/fifo_128x32.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/fifo_128x4.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/fifo_128x64.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/last_gen.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/mstr_cntrl.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/mstr_fifo_cntrl.vhd
stratix_pci_kit-v1.0.0/reference_design/vhdl/pci_local/mstr_perf.vhd
stratix_pci_ki

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