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文件名称:aes-core

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    85.98kb
  • 已下载：
    1次
  • 提 供 者：
    fuj****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.　
相关搜索： aes verilog AES AES core

(系统自动生成,下载前可以参看下载内容)

下载文件列表

aes_core/bench/CVS/Entries
aes_core/bench/CVS/Entries.Extra
aes_core/bench/CVS/Entries.Extra.Old
aes_core/bench/CVS/Entries.Log
aes_core/bench/CVS/Entries.Old
aes_core/bench/CVS/Repository
aes_core/bench/CVS/Root
aes_core/bench/CVS/Template
aes_core/bench/verilog/CVS/Entries
aes_core/bench/verilog/CVS/Entries.Extra
aes_core/bench/verilog/CVS/Entries.Extra.Old
aes_core/bench/verilog/CVS/Entries.Old
aes_core/bench/verilog/CVS/Repository
aes_core/bench/verilog/CVS/Root
aes_core/bench/verilog/CVS/Template
aes_core/bench/verilog/test_bench_top.v
aes_core/CVS/Entries
aes_core/CVS/Entries.Extra
aes_core/CVS/Entries.Extra.Old
aes_core/CVS/Entries.Log
aes_core/CVS/Entries.Old
aes_core/CVS/Repository
aes_core/CVS/Root
aes_core/CVS/Template
aes_core/doc/aes.pdf
aes_core/doc/CVS/Entries
aes_core/doc/CVS/Entries.Extra
aes_core/doc/CVS/Entries.Extra.Old
aes_core/doc/CVS/Entries.Old
aes_core/doc/CVS/Repository
aes_core/doc/CVS/Root
aes_core/doc/CVS/Template
aes_core/readme.txt
aes_core/rtl/CVS/Entries
aes_core/rtl/CVS/Entries.Extra
aes_core/rtl/CVS/Entries.Extra.Old
aes_core/rtl/CVS/Entries.Log
aes_core/rtl/CVS/Entries.Old
aes_core/rtl/CVS/Repository
aes_core/rtl/CVS/Root
aes_core/rtl/CVS/Template
aes_core/rtl/verilog/aes_cipher_top.v
aes_core/rtl/verilog/aes_inv_cipher_top.v
aes_core/rtl/verilog/aes_inv_sbox.v
aes_core/rtl/verilog/aes_key_expand_128.v
aes_core/rtl/verilog/aes_rcon.v
aes_core/rtl/verilog/aes_sbox.v
aes_core/rtl/verilog/CVS/Entries
aes_core/rtl/verilog/CVS/Entries.Extra
aes_core/rtl/verilog/CVS/Entries.Extra.Old
aes_core/rtl/verilog/CVS/Entries.Old
aes_core/rtl/verilog/CVS/Repository
aes_core/rtl/verilog/CVS/Root
aes_core/rtl/verilog/CVS/Template
aes_core/rtl/verilog/timescale.v
aes_core/sim/CVS/Entries
aes_core/sim/CVS/Entries.Extra
aes_core/sim/CVS/Entries.Extra.Old
aes_core/sim/CVS/Entries.Log
aes_core/sim/CVS/Entries.Old
aes_core/sim/CVS/Repository
aes_core/sim/CVS/Root
aes_core/sim/CVS/Template
aes_core/sim/rtl_sim/bin/CVS/Entries
aes_core/sim/rtl_sim/bin/CVS/Entries.Extra
aes_core/sim/rtl_sim/bin/CVS/Entries.Extra.Old
aes_core/sim/rtl_sim/bin/CVS/Entries.Old
aes_core/sim/rtl_sim/bin/CVS/Repository
aes_core/sim/rtl_sim/bin/CVS/Root
aes_core/sim/rtl_sim/bin/CVS/Template
aes_core/sim/rtl_sim/bin/Makefile
aes_core/sim/rtl_sim/CVS/Entries
aes_core/sim/rtl_sim/CVS/Entries.Extra
aes_core/sim/rtl_sim/CVS/Entries.Extra.Old
aes_core/sim/rtl_sim/CVS/Entries.Log
aes_core/sim/rtl_sim/CVS/Entries.Old
aes_core/sim/rtl_sim/CVS/Repository
aes_core/sim/rtl_sim/CVS/Root
aes_core/sim/rtl_sim/CVS/Template
aes_core/sim/rtl_sim/run/CVS/Entries
aes_core/sim/rtl_sim/run/CVS/Entries.Extra
aes_core/sim/rtl_sim/run/CVS/Entries.Extra.Old
aes_core/sim/rtl_sim/run/CVS/Entries.Log
aes_core/sim/rtl_sim/run/CVS/Entries.Old
aes_core/sim/rtl_sim/run/CVS/Repository
aes_core/sim/rtl_sim/run/CVS/Root
aes_core/sim/rtl_sim/run/CVS/Template
aes_core/sim/rtl_sim/run/waves/CVS/Entries
aes_core/sim/rtl_sim/run/waves/CVS/Entries.Extra
aes_core/sim/rtl_sim/run/waves/CVS/Entries.Extra.Old
aes_core/sim/rtl_sim/run/waves/CVS/Entries.Old
aes_core/sim/rtl_sim/run/waves/CVS/Repository
aes_core/sim/rtl_sim/run/waves/CVS/Root
aes_core/sim/rtl_sim/run/waves/CVS/Template
aes_core/sim/rtl_sim/run/waves/waves.do
aes_core/syn/bin/comp.dc
aes_core/syn/bin/CVS/Entries
aes_core/syn/bin/CVS/Entries.Extra
aes_core/syn/bin/CVS/Entries.Extra.Old
aes_core/syn/bin/CVS/Entries.Old
aes_core/syn/bin/CVS/Repository
aes_core/syn/bin/CVS/Root
aes_core/syn/bin/CVS/Template
aes_core/syn/bin/design_spec.dc
aes_core/syn/bin/lib_spec.dc
aes_core/syn/bin/read.dc
aes_core/syn/CVS/Entries
aes_core/syn/CVS/Entries.Extra
aes_core/syn/CVS/Entries.Extra.Old
aes_core/syn/CVS/Entries.Log
aes_core/syn/CVS/Entries.Old
aes_core/syn/CVS/Repository
aes_core/syn/CVS/Root
aes_core/syn/CVS/Template
aes_core/vim_session.vim
aes_core/sim/rtl_sim/run/waves/CVS
aes_core/sim/rtl_sim/bin/CVS
aes_core/sim/rtl_sim/run/CVS
aes_core/sim/rtl_sim/run/waves
aes_core/bench/verilog/CVS
aes_core/rtl/verilog/CVS
aes_core/sim/rtl_sim/bin
aes_core/sim/rtl_sim/CVS
aes_core/sim/rtl_sim/run
aes_core/syn/bin/CVS
aes_core/bench/CVS
aes_core/bench/verilog
aes_core/doc/CVS
aes_core/rtl/CVS
aes_core/rtl/verilog
aes_core/sim/CVS
aes_core/sim/rtl_sim
aes_core/syn/bin
aes_core/syn/CVS
aes_core/bench
aes_core/CVS
aes_core/doc
aes_core/rtl
aes_core/sim
aes_core/syn
aes_core

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