文件名称:FPGAyuandaima
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- 上传时间:2012-11-16
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文件大小:282.53kb
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我们实验室资料,对于学习FPGA的很有帮助,使用的verilog语言来编程-Our laboratory data, very helpful for learning FPGA, using the verilog language programming
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下载文件列表
FPGAyuandaima/Verilog代码/c10/10-2/mult.xco
FPGAyuandaima/Verilog代码/c10/10-2/mult.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-2/mydds.xco
FPGAyuandaima/Verilog代码/c10/10-2/mydds.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-2/square_syn.v
FPGAyuandaima/Verilog代码/c10/10-2/square_syn.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/coastas_dds.v
FPGAyuandaima/Verilog代码/c10/10-4/coastas_dds.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_lf.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_lf.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_loop.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_loop.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_lpf.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_lpf.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_mult.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_mult.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/err_mult.v
FPGAyuandaima/Verilog代码/c10/10-4/err_mult.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/fir_lpf.xco
FPGAyuandaima/Verilog代码/c10/10-4/fir_lpf.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-4/mult.xco
FPGAyuandaima/Verilog代码/c10/10-4/mult.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-4/my_dds.xco
FPGAyuandaima/Verilog代码/c10/10-4/my_dds.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-6/dearly_sub.v
FPGAyuandaima/Verilog代码/c10/10-6/dearly_sub.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/dedds.v
FPGAyuandaima/Verilog代码/c10/10-6/dedds.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/delay_early_gate.v
FPGAyuandaima/Verilog代码/c10/10-6/delay_early_gate.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/de_mult.xco
FPGAyuandaima/Verilog代码/c10/10-6/de_mult.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-6/eddds.xco
FPGAyuandaima/Verilog代码/c10/10-6/eddds.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-6/iir.v
FPGAyuandaima/Verilog代码/c10/10-6/iir.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/iir1.v
FPGAyuandaima/Verilog代码/c10/10-6/iir1.v.!ut
FPGAyuandaima/Verilog代码/c10/10-8/baker.v
FPGAyuandaima/Verilog代码/c10/10-8/baker.v.!ut
FPGAyuandaima/Verilog代码/c11/11-10/div16.xco
FPGAyuandaima/Verilog代码/c11/11-10/div16.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/fir_rls.v
FPGAyuandaima/Verilog代码/c11/11-10/fir_rls.v.!ut
FPGAyuandaima/Verilog代码/c11/11-10/rlsmult.xco
FPGAyuandaima/Verilog代码/c11/11-10/rlsmult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg25.xco
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg25.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg28.xco
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg28.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg3.xco
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg3.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-12/dfe_filter.v
FPGAyuandaima/Verilog代码/c11/11-12/dfe_filter.v.!ut
FPGAyuandaima/Verilog代码/c11/11-12/dfe_mult.xco
FPGAyuandaima/Verilog代码/c11/11-12/dfe_mult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/aa_adder.xco
FPGAyuandaima/Verilog代码/c11/11-14/aa_adder.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/aa_bram.xco
FPGAyuandaima/Verilog代码/c11/11-14/aa_bram.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/aa_cmult.xco
FPGAyuandaima/Verilog代码/c11/11-14/aa_cmult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/ad_a.v
FPGAyuandaima/Verilog代码/c11/11-14/ad_a.v.!ut
FPGAyuandaima/Verilog代码/c11/11-14/shift16.xco
FPGAyuandaima/Verilog代码/c11/11-14/shift16.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-2/fir_lms.v
FPGAyuandaima/Verilog代码/c11/11-2/fir_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-3/fir_pipline_lms.v
FPGAyuandaima/Verilog代码/c11/11-3/fir_pipline_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-3/lmsmult.xco
FPGAyuandaima/Verilog代码/c11/11-3/lmsmult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-5/mult.xco
FPGAyuandaima/Verilog代码/c11/11-5/mult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-5/shiftreg4.xco
FPGAyuandaima/Verilog代码/c11/11-5/shiftreg4.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-5/sign_fir_lms.v
FPGAyuandaima/Verilog代码/c11/11-5/sign_fir_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/blockconnect.v
FPGAyuandaima/Verilog代码/c11/11-8/blockconnect.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/cmult.v
FPGAyuandaima/Verilog代码/c11/11-8/cmult.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/coe_updata.v
FPGAyuandaima/Verilog代码/c11/11-8/coe_updata.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/complex_mult.xco
FPGAyuandaima/Verilog代码/c11/11-8/complex_mult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/fft_block.v
FPGAyuandaima/Verilog代码/c11/11-8/fft_block.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/fft_block_lms.v
FPGAyuandaima/Verilog代码/c11/11-8/fft_block_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/fft_w16_p32.xco
FPGAyuandaima/Verilog代码/c11/11-8/fft_w16_p32.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/gonge.v
FPGAyuandaima/Verilog代码/c11/11-8/gonge.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/ifft_block.v
FPGAyuandaima/Verilog代码/c11/11-8/ifft_block.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/insert.v
FPGAyuandaima/Verilog代码/c11/11-8/insert.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/save_sub.v
FPGAyuandaima/Verilog代码/c11/11-8/save_sub.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg.xco
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg3.xco
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg3.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/shift_reg2.xco
FPGAyuandaima/Verilog代码/c11/11-8/shift_reg2.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/srl16_w16_d16.xco
FPGAyuandaima/Verilog代码/c11/11-8/srl16_w16_d16.xc
FPGAyuandaima/Verilog代码/c10/10-2/mult.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-2/mydds.xco
FPGAyuandaima/Verilog代码/c10/10-2/mydds.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-2/square_syn.v
FPGAyuandaima/Verilog代码/c10/10-2/square_syn.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/coastas_dds.v
FPGAyuandaima/Verilog代码/c10/10-4/coastas_dds.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_lf.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_lf.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_loop.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_loop.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_lpf.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_lpf.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/costas_mult.v
FPGAyuandaima/Verilog代码/c10/10-4/costas_mult.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/err_mult.v
FPGAyuandaima/Verilog代码/c10/10-4/err_mult.v.!ut
FPGAyuandaima/Verilog代码/c10/10-4/fir_lpf.xco
FPGAyuandaima/Verilog代码/c10/10-4/fir_lpf.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-4/mult.xco
FPGAyuandaima/Verilog代码/c10/10-4/mult.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-4/my_dds.xco
FPGAyuandaima/Verilog代码/c10/10-4/my_dds.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-6/dearly_sub.v
FPGAyuandaima/Verilog代码/c10/10-6/dearly_sub.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/dedds.v
FPGAyuandaima/Verilog代码/c10/10-6/dedds.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/delay_early_gate.v
FPGAyuandaima/Verilog代码/c10/10-6/delay_early_gate.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/de_mult.xco
FPGAyuandaima/Verilog代码/c10/10-6/de_mult.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-6/eddds.xco
FPGAyuandaima/Verilog代码/c10/10-6/eddds.xco.!ut
FPGAyuandaima/Verilog代码/c10/10-6/iir.v
FPGAyuandaima/Verilog代码/c10/10-6/iir.v.!ut
FPGAyuandaima/Verilog代码/c10/10-6/iir1.v
FPGAyuandaima/Verilog代码/c10/10-6/iir1.v.!ut
FPGAyuandaima/Verilog代码/c10/10-8/baker.v
FPGAyuandaima/Verilog代码/c10/10-8/baker.v.!ut
FPGAyuandaima/Verilog代码/c11/11-10/div16.xco
FPGAyuandaima/Verilog代码/c11/11-10/div16.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/fir_rls.v
FPGAyuandaima/Verilog代码/c11/11-10/fir_rls.v.!ut
FPGAyuandaima/Verilog代码/c11/11-10/rlsmult.xco
FPGAyuandaima/Verilog代码/c11/11-10/rlsmult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg25.xco
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg25.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg28.xco
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg28.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg3.xco
FPGAyuandaima/Verilog代码/c11/11-10/shiftreg3.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-12/dfe_filter.v
FPGAyuandaima/Verilog代码/c11/11-12/dfe_filter.v.!ut
FPGAyuandaima/Verilog代码/c11/11-12/dfe_mult.xco
FPGAyuandaima/Verilog代码/c11/11-12/dfe_mult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/aa_adder.xco
FPGAyuandaima/Verilog代码/c11/11-14/aa_adder.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/aa_bram.xco
FPGAyuandaima/Verilog代码/c11/11-14/aa_bram.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/aa_cmult.xco
FPGAyuandaima/Verilog代码/c11/11-14/aa_cmult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-14/ad_a.v
FPGAyuandaima/Verilog代码/c11/11-14/ad_a.v.!ut
FPGAyuandaima/Verilog代码/c11/11-14/shift16.xco
FPGAyuandaima/Verilog代码/c11/11-14/shift16.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-2/fir_lms.v
FPGAyuandaima/Verilog代码/c11/11-2/fir_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-3/fir_pipline_lms.v
FPGAyuandaima/Verilog代码/c11/11-3/fir_pipline_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-3/lmsmult.xco
FPGAyuandaima/Verilog代码/c11/11-3/lmsmult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-5/mult.xco
FPGAyuandaima/Verilog代码/c11/11-5/mult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-5/shiftreg4.xco
FPGAyuandaima/Verilog代码/c11/11-5/shiftreg4.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-5/sign_fir_lms.v
FPGAyuandaima/Verilog代码/c11/11-5/sign_fir_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/blockconnect.v
FPGAyuandaima/Verilog代码/c11/11-8/blockconnect.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/cmult.v
FPGAyuandaima/Verilog代码/c11/11-8/cmult.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/coe_updata.v
FPGAyuandaima/Verilog代码/c11/11-8/coe_updata.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/complex_mult.xco
FPGAyuandaima/Verilog代码/c11/11-8/complex_mult.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/fft_block.v
FPGAyuandaima/Verilog代码/c11/11-8/fft_block.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/fft_block_lms.v
FPGAyuandaima/Verilog代码/c11/11-8/fft_block_lms.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/fft_w16_p32.xco
FPGAyuandaima/Verilog代码/c11/11-8/fft_w16_p32.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/gonge.v
FPGAyuandaima/Verilog代码/c11/11-8/gonge.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/ifft_block.v
FPGAyuandaima/Verilog代码/c11/11-8/ifft_block.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/insert.v
FPGAyuandaima/Verilog代码/c11/11-8/insert.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/save_sub.v
FPGAyuandaima/Verilog代码/c11/11-8/save_sub.v.!ut
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg.xco
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg3.xco
FPGAyuandaima/Verilog代码/c11/11-8/shiftreg3.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/shift_reg2.xco
FPGAyuandaima/Verilog代码/c11/11-8/shift_reg2.xco.!ut
FPGAyuandaima/Verilog代码/c11/11-8/srl16_w16_d16.xco
FPGAyuandaima/Verilog代码/c11/11-8/srl16_w16_d16.xc
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