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文件名称:VGA_265

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    501.97kb
  • 已下载：
    0次
  • 提 供 者：
    老***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Verilog语言描述的VGA显示实验，主要目的是在显示屏上显示256色，对初学者有用-Verilog language descr iption of the VGA display experiment, the main purpose is to display 256 colors on the screen, useful for beginners
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VGA_265/
VGA_265/VGA_256.asm.rpt
VGA_265/VGA_256.cdf
VGA_265/VGA_256.done
VGA_265/VGA_256.dpf
VGA_265/VGA_256.eda.rpt
VGA_265/VGA_256.fit.rpt
VGA_265/VGA_256.fit.smsg
VGA_265/VGA_256.fit.summary
VGA_265/VGA_256.flow.rpt
VGA_265/VGA_256.map.rpt
VGA_265/VGA_256.map.summary
VGA_265/VGA_256.pin
VGA_265/VGA_256.pof
VGA_265/VGA_256.qpf
VGA_265/VGA_256.qsf
VGA_265/VGA_256.qws
VGA_265/VGA_256.sof
VGA_265/VGA_256.tan.rpt
VGA_265/VGA_256.tan.summary
VGA_265/VGA_256.v
VGA_265/VGA_256.v.bak
VGA_265/VGA_256_nativelink_simulation.rpt
VGA_265/db/
VGA_265/db/VGA_256.(0).cnf.cdb
VGA_265/db/VGA_256.(0).cnf.hdb
VGA_265/db/VGA_256.asm.qmsg
VGA_265/db/VGA_256.asm.rdb
VGA_265/db/VGA_256.cbx.xml
VGA_265/db/VGA_256.cmp.bpm
VGA_265/db/VGA_256.cmp.cdb
VGA_265/db/VGA_256.cmp.ecobp
VGA_265/db/VGA_256.cmp.hdb
VGA_265/db/VGA_256.cmp.kpt
VGA_265/db/VGA_256.cmp.logdb
VGA_265/db/VGA_256.cmp.rdb
VGA_265/db/VGA_256.cmp.tdb
VGA_265/db/VGA_256.cmp0.ddb
VGA_265/db/VGA_256.cmp_merge.kpt
VGA_265/db/VGA_256.db_info
VGA_265/db/VGA_256.eco.cdb
VGA_265/db/VGA_256.eda.qmsg
VGA_265/db/VGA_256.fit.qmsg
VGA_265/db/VGA_256.hier_info
VGA_265/db/VGA_256.hif
VGA_265/db/VGA_256.lpc.html
VGA_265/db/VGA_256.lpc.rdb
VGA_265/db/VGA_256.lpc.txt
VGA_265/db/VGA_256.map.bpm
VGA_265/db/VGA_256.map.cdb
VGA_265/db/VGA_256.map.ecobp
VGA_265/db/VGA_256.map.hdb
VGA_265/db/VGA_256.map.kpt
VGA_265/db/VGA_256.map.logdb
VGA_265/db/VGA_256.map.qmsg
VGA_265/db/VGA_256.map_bb.cdb
VGA_265/db/VGA_256.map_bb.hdb
VGA_265/db/VGA_256.map_bb.logdb
VGA_265/db/VGA_256.pre_map.cdb
VGA_265/db/VGA_256.pre_map.hdb
VGA_265/db/VGA_256.rtlv.hdb
VGA_265/db/VGA_256.rtlv_sg.cdb
VGA_265/db/VGA_256.rtlv_sg_swap.cdb
VGA_265/db/VGA_256.sgdiff.cdb
VGA_265/db/VGA_256.sgdiff.hdb
VGA_265/db/VGA_256.sld_design_entry.sci
VGA_265/db/VGA_256.sld_design_entry_dsc.sci
VGA_265/db/VGA_256.smart_action.txt
VGA_265/db/VGA_256.syn_hier_info
VGA_265/db/VGA_256.tan.qmsg
VGA_265/db/VGA_256.tis_db_list.ddb
VGA_265/db/VGA_256.tmw_info
VGA_265/db/logic_util_heursitic.dat
VGA_265/db/prev_cmp_VGA_256.asm.qmsg
VGA_265/db/prev_cmp_VGA_256.eda.qmsg
VGA_265/db/prev_cmp_VGA_256.fit.qmsg
VGA_265/db/prev_cmp_VGA_256.map.qmsg
VGA_265/db/prev_cmp_VGA_256.qmsg
VGA_265/db/prev_cmp_VGA_256.tan.qmsg
VGA_265/incremental_db/
VGA_265/incremental_db/README
VGA_265/incremental_db/compiled_partitions/
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.cmp.cdb
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.cmp.dfp
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.cmp.hdb
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.cmp.kpt
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.cmp.logdb
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.cmp.rcfdb
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.cmp.re.rcfdb
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.map.cdb
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.map.dpi
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.map.hdb
VGA_265/incremental_db/compiled_partitions/VGA_256.root_partition.map.kpt
VGA_265/output_file.jic
VGA_265/output_file.map
VGA_265/simulation/
VGA_265/simulation/modelsim/
VGA_265/simulation/modelsim/VGA_256.sft
VGA_265/simulation/modelsim/VGA_256.vo
VGA_265/simulation/modelsim/VGA_256.vt
VGA_265/simulation/modelsim/VGA_256.vt.bak
VGA_265/simulation/modelsim/VGA_256_modelsim.xrf
VGA_265/simulation/modelsim/VGA_256_run_msim_rtl_verilog.do
VGA_265/simulation/modelsim/VGA_256_run_msim_rtl_verilog.do.bak
VGA_265/simulation/modelsim/VGA_256_run_msim_rtl_verilog.do.bak1
VGA_265/simulation/modelsim/VGA_256_run_msim_rtl_verilog.do.bak2
VGA_265/simulation/modelsim/VGA_256_run_msim_rtl_verilog.do.bak3
VGA_265/simulation/modelsim/VGA_256_v.sdo
VGA_265/simulation/modelsim/modelsim.ini
VGA_265/simulation/modelsim/msim_transcript
VGA_265/simulation/modelsim/rtl_work/
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256/
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256/_primary.dat
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256/_primary.dbs
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256/_primary.vhd
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256/verilog.prw
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256/verilog.psm
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256_vlg_tst/
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256_vlg_tst/_primary.dat
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256_vlg_tst/_primary.dbs
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256_vlg_tst/_primary.vhd
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256_vlg_tst/verilog.prw
VGA_265/simulation/modelsim/rtl_work/@v@g@a_256_vlg_tst/verilog.psm
VGA_265/simulation/modelsim/rtl_work/_info
VGA_265/simulation/modelsim/rtl_work/_temp/
VGA_265/simulation/modelsim/rtl_work/_vmake

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