1．用VHDL设计具有清除端、使能端，计数范围为0~999的计数器，输出为8421BCD码；

2．用VHDL设计十进制计数器（BCD_CNT）模块、七段显示译码器电路（BEC_LED）模块和分时总线切换电路（SCAN）模块。

3．用MAX+plusⅡ进行时序仿真。

-1. VHDL design with a clear end to end so that the count range of 0 to 999 in the counter, the output is 8421BCD code　2. Decimal counter with VHDL Design (BCD_CNT) modules, seven segment display decoder circuit (BEC_LED) modules and sharing the bus switching circuit (SCAN) module. 3. With MAX+ plus Ⅱ timing simulation.