文件名称:AN123
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:4.27mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
AMBA Application Note: AN123 - Logic Tile IT1 GPIO example design.
-Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1 board.
The following board combinations are supported:
Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1
Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1
Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1
Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1
PB926EJ-S+ LT-XC2V6000+ IT1
PB926EJ-S+ LT-XC2V8000+ IT1
Asynchronous and Synchronous bridge modes are supported on the PB926EJ-S with different design images. Asynchronous mode is selected using SW1[3] on the PB926EJ-S.
-Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1 board.
The following board combinations are supported:
Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1
Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1
Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V6000+ IT1
Integrator/CP+ Core Module+ Integrator/IM-LT1+ LT-XC2V8000+ IT1
PB926EJ-S+ LT-XC2V6000+ IT1
PB926EJ-S+ LT-XC2V8000+ IT1
Asynchronous and Synchronous bridge modes are supported on the PB926EJ-S with different design images. Asynchronous mode is selected using SW1[3] on the PB926EJ-S.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
AN123/
AN123/3.7/
AN123/3.7/1/
AN123/3.7/1/boardfiles/
AN123/3.7/1/boardfiles/ab926ejs_skip.brd
AN123/3.7/1/boardfiles/ab_ib2_skip.brd
AN123/3.7/1/boardfiles/an123/
AN123/3.7/1/boardfiles/an123/an123_ltxc2v6000_102cd_integrator_flash_revb_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v6000_102cd_pb926_async_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v6000_102cd_pb926_sync_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v8000_102cd_integrator_flash_revb_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v8000_102cd_pb926_async_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v8000_102cd_pb926_sync_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v6000_async_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v6000_sync_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v8000_async_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v8000_sync_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_integrator_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_integrator_flash_revb_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_pb926_async_flash_reve_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_pb926_sync_flash_reve_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_integrator_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_integrator_flash_revb_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_pb926_async_flash_reve_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_pb926_sync_flash_reve_build1.brd
AN123/3.7/1/boardfiles/ap_skip.brd
AN123/3.7/1/boardfiles/cm_skip.brd
AN123/3.7/1/boardfiles/cm_skip_tap3.brd
AN123/3.7/1/boardfiles/cp_skip.brd
AN123/3.7/1/boardfiles/ct1156_skip.brd
AN123/3.7/1/boardfiles/ct11mpcore_skip.brd
AN123/3.7/1/boardfiles/ct_skip.brd
AN123/3.7/1/boardfiles/eb_skip.brd
AN123/3.7/1/boardfiles/FileList.txt
AN123/3.7/1/boardfiles/imlt3_skip.brd
AN123/3.7/1/boardfiles/irlength_arm.txt
AN123/3.7/1/boardfiles/lgpl.txt
AN123/3.7/1/boardfiles/lt-xc2v4000_hbi0102/
AN123/3.7/1/boardfiles/lt-xc2v4000_hbi0102/ltxc2v4000_102cd_xc9572xl_bytestreamer_build3.svf
AN123/3.7/1/boardfiles/ltxc2v4000_102cd_bytestreamer_build3.brd
AN123/3.7/1/boardfiles/lt_skip.brd
AN123/3.7/1/boardfiles/multi-ice/
AN123/3.7/1/boardfiles/multi-ice/multi-ice_config_file_creator.xls
AN123/3.7/1/boardfiles/pb926ej-s_skip.brd
AN123/3.7/1/boardfiles/progcards.exe
AN123/3.7/1/boardfiles/progcards.pdf
AN123/3.7/1/boardfiles/progcards_multiice.exe
AN123/3.7/1/boardfiles/progcards_rvi.exe
AN123/3.7/1/boardfiles/progcards_rvi.pdf
AN123/3.7/1/boardfiles/progcards_usb.exe
AN123/3.7/1/boardfiles/prog_engine_1_4
AN123/3.7/1/boardfiles/prog_engine_1_5
AN123/3.7/1/boardfiles/prog_engine_3_0
AN123/3.7/1/boardfiles/rvicomms.dll
AN123/3.7/1/boardfiles/RVI_Progcards_ReadMe.txt
AN123/3.7/1/boardfiles/stlport_vc645.dll
AN123/3.7/1/boardfiles/tapid.arm
AN123/3.7/1/boardfiles/UsingProgCardsUtility.pdf
AN123/3.7/1/boardfiles/v4lt_skip.brd
AN123/3.7/1/boardfiles/VersatileUpgradingHardware.txt
AN123/3.7/1/boardfiles/via/
AN123/3.7/1/boardfiles/via/ltxc2v4000_102cd_xc2v6000_via_build1.bit
AN123/3.7/1/boardfiles/via/ltxc2v4000_102cd_xc2v8000_via_build1.bit
AN123/3.7/1/boardfiles/ZThread-1_5_1_tar.gz
AN123/3.7/1/boardfiles/zthread.dll
AN123/3.7/1/disable.xml
AN123/3.7/1/docs/
AN123/3.7/1/docs/AN123_Versatile_IT1_Example_Design.pdf
AN123/3.7/1/docs/licence.pdf
AN123/3.7/1/docs/readme.txt
AN123/3.7/1/docs/revision_history.txt
AN123/3.7/1/enable.xml
AN123/3.7/1/logical/
AN123/3.7/1/logical/virtex2_integrator_fpga/
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHB2APB.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBAPBSys.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBDecoder.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBDefaultSlave.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AhbGPIOSlave.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBMuxS2M.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBTopLevel.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBZBTRAM.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBClockArbiter.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBClocks.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBIntcon.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBRegs.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/MuxP2B.v
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHB2APB.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBAPBSys.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBDecoder.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBDefaultSlave.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AhbGPIOSlave.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBMuxS2M.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBTopLevel.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBZBTRAM.vhd
AN123/3.7/1/logical/virt
AN123/3.7/
AN123/3.7/1/
AN123/3.7/1/boardfiles/
AN123/3.7/1/boardfiles/ab926ejs_skip.brd
AN123/3.7/1/boardfiles/ab_ib2_skip.brd
AN123/3.7/1/boardfiles/an123/
AN123/3.7/1/boardfiles/an123/an123_ltxc2v6000_102cd_integrator_flash_revb_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v6000_102cd_pb926_async_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v6000_102cd_pb926_sync_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v8000_102cd_integrator_flash_revb_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v8000_102cd_pb926_async_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123/an123_ltxc2v8000_102cd_pb926_sync_flash_reve_build1.bit
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v6000_async_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v6000_sync_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v8000_async_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v4000_102c_xc2v8000_sync_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_integrator_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_integrator_flash_revb_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_pb926_async_flash_reve_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v6000_102cd_pb926_sync_flash_reve_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_integrator_customer_rebuild.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_integrator_flash_revb_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_pb926_async_flash_reve_build1.brd
AN123/3.7/1/boardfiles/an123_ltxc2v8000_102cd_pb926_sync_flash_reve_build1.brd
AN123/3.7/1/boardfiles/ap_skip.brd
AN123/3.7/1/boardfiles/cm_skip.brd
AN123/3.7/1/boardfiles/cm_skip_tap3.brd
AN123/3.7/1/boardfiles/cp_skip.brd
AN123/3.7/1/boardfiles/ct1156_skip.brd
AN123/3.7/1/boardfiles/ct11mpcore_skip.brd
AN123/3.7/1/boardfiles/ct_skip.brd
AN123/3.7/1/boardfiles/eb_skip.brd
AN123/3.7/1/boardfiles/FileList.txt
AN123/3.7/1/boardfiles/imlt3_skip.brd
AN123/3.7/1/boardfiles/irlength_arm.txt
AN123/3.7/1/boardfiles/lgpl.txt
AN123/3.7/1/boardfiles/lt-xc2v4000_hbi0102/
AN123/3.7/1/boardfiles/lt-xc2v4000_hbi0102/ltxc2v4000_102cd_xc9572xl_bytestreamer_build3.svf
AN123/3.7/1/boardfiles/ltxc2v4000_102cd_bytestreamer_build3.brd
AN123/3.7/1/boardfiles/lt_skip.brd
AN123/3.7/1/boardfiles/multi-ice/
AN123/3.7/1/boardfiles/multi-ice/multi-ice_config_file_creator.xls
AN123/3.7/1/boardfiles/pb926ej-s_skip.brd
AN123/3.7/1/boardfiles/progcards.exe
AN123/3.7/1/boardfiles/progcards.pdf
AN123/3.7/1/boardfiles/progcards_multiice.exe
AN123/3.7/1/boardfiles/progcards_rvi.exe
AN123/3.7/1/boardfiles/progcards_rvi.pdf
AN123/3.7/1/boardfiles/progcards_usb.exe
AN123/3.7/1/boardfiles/prog_engine_1_4
AN123/3.7/1/boardfiles/prog_engine_1_5
AN123/3.7/1/boardfiles/prog_engine_3_0
AN123/3.7/1/boardfiles/rvicomms.dll
AN123/3.7/1/boardfiles/RVI_Progcards_ReadMe.txt
AN123/3.7/1/boardfiles/stlport_vc645.dll
AN123/3.7/1/boardfiles/tapid.arm
AN123/3.7/1/boardfiles/UsingProgCardsUtility.pdf
AN123/3.7/1/boardfiles/v4lt_skip.brd
AN123/3.7/1/boardfiles/VersatileUpgradingHardware.txt
AN123/3.7/1/boardfiles/via/
AN123/3.7/1/boardfiles/via/ltxc2v4000_102cd_xc2v6000_via_build1.bit
AN123/3.7/1/boardfiles/via/ltxc2v4000_102cd_xc2v8000_via_build1.bit
AN123/3.7/1/boardfiles/ZThread-1_5_1_tar.gz
AN123/3.7/1/boardfiles/zthread.dll
AN123/3.7/1/disable.xml
AN123/3.7/1/docs/
AN123/3.7/1/docs/AN123_Versatile_IT1_Example_Design.pdf
AN123/3.7/1/docs/licence.pdf
AN123/3.7/1/docs/readme.txt
AN123/3.7/1/docs/revision_history.txt
AN123/3.7/1/enable.xml
AN123/3.7/1/logical/
AN123/3.7/1/logical/virtex2_integrator_fpga/
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHB2APB.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBAPBSys.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBDecoder.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBDefaultSlave.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AhbGPIOSlave.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBMuxS2M.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBTopLevel.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/AHBZBTRAM.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBClockArbiter.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBClocks.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBIntcon.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/APBRegs.v
AN123/3.7/1/logical/virtex2_integrator_fpga/verilog/MuxP2B.v
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHB2APB.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBAPBSys.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBDecoder.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBDefaultSlave.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AhbGPIOSlave.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBMuxS2M.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBTopLevel.vhd
AN123/3.7/1/logical/virtex2_integrator_fpga/vhdl/AHBZBTRAM.vhd
AN123/3.7/1/logical/virt
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.