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文件名称:Verilog-Digital-System-Design

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    8.48mb
  • 已下载：
    0次
  • 提 供 者：
    鲁****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
相关搜索： rtl verification

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Designs/Chapter 1/chap1counter.v
Designs/Chapter 1/Chap1CounterTester.v
Designs/Chapter 1/confn.v
Designs/Chapter 1/dlatch.v
Designs/Chapter 1/dreg.v
Designs/Chapter 1/latchtest.v
Designs/Chapter 1/parity.v
Designs/Chapter 1/srlatch.v
Designs/Chapter 1
Designs/Chapter 2/ALU.v
Designs/Chapter 2/ALUTester.v
Designs/Chapter 2/Counter4.v
Designs/Chapter 2/Counter4Tester.v
Designs/Chapter 2/Detector110.v
Designs/Chapter 2/Detector110Tester.v
Designs/Chapter 2/flop.v
Designs/Chapter 2/FlopTester.v
Designs/Chapter 2/MultiplexerA.v
Designs/Chapter 2/MultiplexerA2to1.v
Designs/Chapter 2/MultiplexerB.v
Designs/Chapter 2/MultiplexerC.v
Designs/Chapter 2/MultiplexerD.v
Designs/Chapter 2/MultiplexerE.v
Designs/Chapter 2/MultiplexerTester.v
Designs/Chapter 2/Mux8.v
Designs/Chapter 2/Mux8Tester.v
Designs/Chapter 2/ShiftRegister.v
Designs/Chapter 2/ShiftRegisterTester.v
Designs/Chapter 2/Synchronizer.v
Designs/Chapter 2/SynchronizerTester.v
Designs/Chapter 2
Designs/Chapter 3/Flipflop.v
Designs/Chapter 3/FlipflopAssign.v
Designs/Chapter 3/FlipflopAssignTester.v
Designs/Chapter 3/FlipflopTester.v
Designs/Chapter 3/Fulladder.v
Designs/Chapter 3/FulladderTester.v
Designs/Chapter 3/MemoryTest.v
Designs/Chapter 3/Mux2ti1TestA.v
Designs/Chapter 3/Mux2to1.v
Designs/Chapter 3/Mux2to1BTest.v
Designs/Chapter 3/Mux2to1Multiple.v
Designs/Chapter 3/Mux2to1Net.v
Designs/Chapter 3/Mux2to1TestC.v
Designs/Chapter 3/Mux2to1Tester.v
Designs/Chapter 3/NumberTest.v
Designs/Chapter 3/OperatorTest.v
Designs/Chapter 3/SignTest.v
Designs/Chapter 3
Designs/Chapter 4/add_1bit.v
Designs/Chapter 4/add_1bit_blocking.v
Designs/Chapter 4/add_1bit_f.v
Designs/Chapter 4/add_1bit_p.v
Designs/Chapter 4/add_1bit_p2p.v
Designs/Chapter 4/add_1bit_p_named.v
Designs/Chapter 4/add_4bit.v
Designs/Chapter 4/add_4bit_gen.v
Designs/Chapter 4/add_4bit_genif.v
Designs/Chapter 4/add_4bit_p2p.v
Designs/Chapter 4/add_4bit_vec.v
Designs/Chapter 4/Anding.v
Designs/Chapter 4/AndingTest.v
Designs/Chapter 4/maj3_p.v
Designs/Chapter 4/multi_alu.v
Designs/Chapter 4/multi_alu_test.v
Designs/Chapter 4/priority_encoder.v
Designs/Chapter 4/quad_mux2_1.v
Designs/Chapter 4/test_add_1bit_blocking.v
Designs/Chapter 4/test_add_1bit_p.v
Designs/Chapter 4/test_add_4bit.v
Designs/Chapter 4/test_maj3_p.v
Designs/Chapter 4/test_priority_encoder.v
Designs/Chapter 4/test_quad_mux2_1.v
Designs/Chapter 4/test_xor3.v
Designs/Chapter 4/TriMux.v
Designs/Chapter 4/TriMuxTest.v
Designs/Chapter 4/xor3_behavioral.v
Designs/Chapter 4/xor3_p.v
Designs/Chapter 4
Designs/Chapter 5/counter.v
Designs/Chapter 5/d_ff.v
Designs/Chapter 5/d_ff_hold.v
Designs/Chapter 5/d_ff_setup.v
Designs/Chapter 5/d_ff_sr_Asynch.v
Designs/Chapter 5/d_ff_sr_Synch.v
Designs/Chapter 5/d_ff__setup_hold_width_period.v
Designs/Chapter 5/gray_ounter.v
Designs/Chapter 5/latch.v
Designs/Chapter 5/latch_p.v
Designs/Chapter 5/latch_w.v
Designs/Chapter 5/lfsr1.v
Designs/Chapter 5/lfsr2.v
Designs/Chapter 5/mealy.dat
Designs/Chapter 5/mealy_detector2.v
Designs/Chapter 5/mealy_detector6.v
Designs/Chapter 5/mealy_detector7.v
Designs/Chapter 5/mem.dat
Designs/Chapter 5/Memory_2Power_M_by_N.v
Designs/Chapter 5/misr.v
Designs/Chapter 5/misrTEST.v
Designs/Chapter 5/moore_detector.v
Designs/Chapter 5/moore_detector3.v
Designs/Chapter 5/moore_detector4.v
Designs/Chapter 5/pla.dat
Designs/Chapter 5/pla.v
Designs/Chapter 5/shift_reg.v
Designs/Chapter 5/sizable_reg.v
Designs/Chapter 5/test_counter.v
Designs/Chapter 5/test_d_ff.v
Designs/Chapter 5/test_d_ff_hold.v
Designs/Chapter 5/test_d_ff_setup2.v
Designs/Chapter 5/test_d_ff_setup_hold_width_period.v
Designs/Chapter 5/Test_d_ff_sr_Synch.v
Designs/Chapter 5/test_gray_counter.v
Designs/Chapter 5/test_latch.v
Designs/Chapter 5/test_latch_p.v
Designs/Chapter 5/test_lfsr1.v
Designs/Chapter 5/test_lfsr2.v
Designs/Chapter 5/test_mealy_detector2.v
Designs/Chapter 5/test_mealy_detector6.v
Designs/Chapter 5/test_mealy_detector7.v
Designs/Chapter 5/Test_Memory_2Power_M_by_N.v
Designs/Chapter 5/test_misr.v
Designs/Chapter 5/test_moore_detector.v
Designs/Chapter 5/test_moore_detector3.v
Designs/Chapter 5/test_moore_detector4.v
Designs/Chapter 5/test_pla.v
Designs/Chapter 5/test_shift_reg.v
Designs/Chapter 5/test_vector_ff.v
Designs/Chapter 5/vector_ff.v
Designs/Chapter 5
Designs/Chapter 6/moore_detector.v
Designs/Chapter 6/moore_detector2.v
Designs/Chapter 6/test1.v
Designs/Chapter 6/test10.v
Designs/Chapter 6/test11.v
Designs/Chapter 6/test12.v
Designs/Chapter 6/test2.v
Designs/Chapter 6/test3.v
Designs/Chapter 6/test6.v
Designs/Chapter 6/test9.v
Designs/Chapter 6
Designs/Chapter 7/an_nmos.v
Designs/Chapter 7/aoi_3d.v
Designs/Chapter 7/barrel_shifter.v
Designs/Chapter 7/barrel_shifter_reg.v
Designs/Chapter 7/cross_couple.v
Designs/Chapter 7/dynamic_cell.v
Designs/Chapter 7/d_latch.v
Designs/Chapter 7/half_reg.v
Designs/Chapter 7/master_slave_dff.v
Designs/Chapter 7/mos_strength.v
Designs/Chapter 7/nand2_1d.v
Designs/Chapter 7/Problem6.v
Designs/Chapter 7/register_4.v
Designs/Chapter 7/shifter.v
Designs/Chapter 7/test_an_nmos.v
Designs/Chapter 7/test_aoi_3d.v
Designs/Chapter 7/test_barrel_shifter.v
Designs/Chapter 7/test_barrel_shif

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