文件名称:vhdl-xiyiji
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- 上传时间:2012-11-16
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文件大小:979.49kb
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基于quartus2的vhdl状态机——洗衣机编程应用,采用EDA自顶向下的设计方法。-The vhdl state machine based quartus2- washing machine programming applications, the EDA top-down design approach.
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下载文件列表
vhdl xiyiji/simulate/clock.vhd
vhdl xiyiji/simulate/clock.vhd.bak
vhdl xiyiji/simulate/count_time.bsf
vhdl xiyiji/simulate/count_time.vhd
vhdl xiyiji/simulate/db/prev_cmp_simulate.asm.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.fit.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.map.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.sim.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.tan.qmsg
vhdl xiyiji/simulate/db/simulate.(0).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(0).cnf.hdb
vhdl xiyiji/simulate/db/simulate.(1).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(1).cnf.hdb
vhdl xiyiji/simulate/db/simulate.(2).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(2).cnf.hdb
vhdl xiyiji/simulate/db/simulate.(3).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(3).cnf.hdb
vhdl xiyiji/simulate/db/simulate.asm.qmsg
vhdl xiyiji/simulate/db/simulate.asm_labs.ddb
vhdl xiyiji/simulate/db/simulate.cbx.xml
vhdl xiyiji/simulate/db/simulate.cmp.cdb
vhdl xiyiji/simulate/db/simulate.cmp.hdb
vhdl xiyiji/simulate/db/simulate.cmp.kpt
vhdl xiyiji/simulate/db/simulate.cmp.logdb
vhdl xiyiji/simulate/db/simulate.cmp.rdb
vhdl xiyiji/simulate/db/simulate.cmp.tdb
vhdl xiyiji/simulate/db/simulate.cmp0.ddb
vhdl xiyiji/simulate/db/simulate.db_info
vhdl xiyiji/simulate/db/simulate.eco.cdb
vhdl xiyiji/simulate/db/simulate.eds_overflow
vhdl xiyiji/simulate/db/simulate.fit.qmsg
vhdl xiyiji/simulate/db/simulate.hier_info
vhdl xiyiji/simulate/db/simulate.hif
vhdl xiyiji/simulate/db/simulate.map.cdb
vhdl xiyiji/simulate/db/simulate.map.hdb
vhdl xiyiji/simulate/db/simulate.map.logdb
vhdl xiyiji/simulate/db/simulate.map.qmsg
vhdl xiyiji/simulate/db/simulate.pre_map.cdb
vhdl xiyiji/simulate/db/simulate.pre_map.hdb
vhdl xiyiji/simulate/db/simulate.rtlv.hdb
vhdl xiyiji/simulate/db/simulate.rtlv_sg.cdb
vhdl xiyiji/simulate/db/simulate.rtlv_sg_swap.cdb
vhdl xiyiji/simulate/db/simulate.sgdiff.cdb
vhdl xiyiji/simulate/db/simulate.sgdiff.hdb
vhdl xiyiji/simulate/db/simulate.sim.cvwf
vhdl xiyiji/simulate/db/simulate.sim.hdb
vhdl xiyiji/simulate/db/simulate.sim.qmsg
vhdl xiyiji/simulate/db/simulate.sim.rdb
vhdl xiyiji/simulate/db/simulate.sld_design_entry.sci
vhdl xiyiji/simulate/db/simulate.sld_design_entry_dsc.sci
vhdl xiyiji/simulate/db/simulate.syn_hier_info
vhdl xiyiji/simulate/db/simulate.tan.qmsg
vhdl xiyiji/simulate/db/simulate.tis_db_list.ddb
vhdl xiyiji/simulate/db/simulate.tmw_info
vhdl xiyiji/simulate/db/wed.wsf
vhdl xiyiji/simulate/incremental_db/compiled_partitions/simulate.root_partition.map.kpt
vhdl xiyiji/simulate/incremental_db/README
vhdl xiyiji/simulate/modein.bsf
vhdl xiyiji/simulate/modein.vhd
vhdl xiyiji/simulate/set.bsf
vhdl xiyiji/simulate/set.vhd
vhdl xiyiji/simulate/simulate.asm.rpt
vhdl xiyiji/simulate/simulate.bdf
vhdl xiyiji/simulate/simulate.done
vhdl xiyiji/simulate/simulate.fit.rpt
vhdl xiyiji/simulate/simulate.fit.smsg
vhdl xiyiji/simulate/simulate.fit.summary
vhdl xiyiji/simulate/simulate.flow.rpt
vhdl xiyiji/simulate/simulate.map.rpt
vhdl xiyiji/simulate/simulate.map.summary
vhdl xiyiji/simulate/simulate.pin
vhdl xiyiji/simulate/simulate.pof
vhdl xiyiji/simulate/simulate.qpf
vhdl xiyiji/simulate/simulate.qsf
vhdl xiyiji/simulate/simulate.qws
vhdl xiyiji/simulate/simulate.sim.rpt
vhdl xiyiji/simulate/simulate.tan.rpt
vhdl xiyiji/simulate/simulate.tan.summary
vhdl xiyiji/simulate/simulate.vwf
vhdl xiyiji/wash/count_time.vhd
vhdl xiyiji/wash/db/prev_cmp_wash.asm.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.fit.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.map.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.tan.qmsg
vhdl xiyiji/wash/db/wash.(0).cnf.cdb
vhdl xiyiji/wash/db/wash.(0).cnf.hdb
vhdl xiyiji/wash/db/wash.(1).cnf.cdb
vhdl xiyiji/wash/db/wash.(1).cnf.hdb
vhdl xiyiji/wash/db/wash.(2).cnf.cdb
vhdl xiyiji/wash/db/wash.(2).cnf.hdb
vhdl xiyiji/wash/db/wash.(3).cnf.cdb
vhdl xiyiji/wash/db/wash.(3).cnf.hdb
vhdl xiyiji/wash/db/wash.(4).cnf.cdb
vhdl xiyiji/wash/db/wash.(4).cnf.hdb
vhdl xiyiji/wash/db/wash.asm.qmsg
vhdl xiyiji/wash/db/wash.asm_labs.ddb
vhdl xiyiji/wash/db/wash.cbx.xml
vhdl xiyiji/wash/db/wash.cmp.cdb
vhdl xiyiji/wash/db/wash.cmp.hdb
vhdl xiyiji/wash/db/wash.cmp.logdb
vhdl xiyiji/wash/db/wash.cmp.rdb
vhdl xiyiji/wash/db/wash.cmp.tdb
vhdl xiyiji/wash/db/wash.cmp0.ddb
vhdl xiyiji/wash/db/wash.dbp
vhdl xiyiji/wash/db/wash.db_info
vhdl xiyiji/wash/db/wash.eco.cdb
vhdl xiyiji/wash/db/wash.fit.qmsg
vhdl xiyiji/wash/db/wash.hier_info
vhdl xiyiji/wash/db/wash.hif
vhdl xiyiji/wash/db/wash.map.cdb
vhdl xiyiji/wash/db/wash.map.hdb
vhdl xiyiji/wash/db/wash.map.logdb
vhdl xiyiji/wash/db/wash.map.qmsg
vhdl xiyiji/wash/db/wash.pre_map.cdb
vhdl xiyiji/wash/db/wash.pre_map.hdb
vhdl xiyiji/wash/db/wash.psp
vhdl xiyiji/wash/db/wash.pss
vhdl xiyiji/wash/db/wash.rtlv.hdb
vhdl xiyiji/wash/db/wash.rtlv_sg.cdb
vhdl xiyiji/wash/db/wash.rtlv_sg_swap.cdb
vhdl xiyiji/wash/db/wash.sgdiff.cdb
vhdl xiyiji/wash/db/wash.sgdiff.hdb
vhdl xiyiji/wash/db/wash.signalprobe.cdb
vhdl xiyiji/wash/db/wash.sld_design_entry.sci
vhdl xiyiji/wash/db/wash.sld_design_entry_dsc.sci
vhdl xiyiji/wash/db/wash.syn_hier_info
vhdl xiyiji/wash/db
vhdl xiyiji/simulate/clock.vhd.bak
vhdl xiyiji/simulate/count_time.bsf
vhdl xiyiji/simulate/count_time.vhd
vhdl xiyiji/simulate/db/prev_cmp_simulate.asm.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.fit.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.map.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.sim.qmsg
vhdl xiyiji/simulate/db/prev_cmp_simulate.tan.qmsg
vhdl xiyiji/simulate/db/simulate.(0).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(0).cnf.hdb
vhdl xiyiji/simulate/db/simulate.(1).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(1).cnf.hdb
vhdl xiyiji/simulate/db/simulate.(2).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(2).cnf.hdb
vhdl xiyiji/simulate/db/simulate.(3).cnf.cdb
vhdl xiyiji/simulate/db/simulate.(3).cnf.hdb
vhdl xiyiji/simulate/db/simulate.asm.qmsg
vhdl xiyiji/simulate/db/simulate.asm_labs.ddb
vhdl xiyiji/simulate/db/simulate.cbx.xml
vhdl xiyiji/simulate/db/simulate.cmp.cdb
vhdl xiyiji/simulate/db/simulate.cmp.hdb
vhdl xiyiji/simulate/db/simulate.cmp.kpt
vhdl xiyiji/simulate/db/simulate.cmp.logdb
vhdl xiyiji/simulate/db/simulate.cmp.rdb
vhdl xiyiji/simulate/db/simulate.cmp.tdb
vhdl xiyiji/simulate/db/simulate.cmp0.ddb
vhdl xiyiji/simulate/db/simulate.db_info
vhdl xiyiji/simulate/db/simulate.eco.cdb
vhdl xiyiji/simulate/db/simulate.eds_overflow
vhdl xiyiji/simulate/db/simulate.fit.qmsg
vhdl xiyiji/simulate/db/simulate.hier_info
vhdl xiyiji/simulate/db/simulate.hif
vhdl xiyiji/simulate/db/simulate.map.cdb
vhdl xiyiji/simulate/db/simulate.map.hdb
vhdl xiyiji/simulate/db/simulate.map.logdb
vhdl xiyiji/simulate/db/simulate.map.qmsg
vhdl xiyiji/simulate/db/simulate.pre_map.cdb
vhdl xiyiji/simulate/db/simulate.pre_map.hdb
vhdl xiyiji/simulate/db/simulate.rtlv.hdb
vhdl xiyiji/simulate/db/simulate.rtlv_sg.cdb
vhdl xiyiji/simulate/db/simulate.rtlv_sg_swap.cdb
vhdl xiyiji/simulate/db/simulate.sgdiff.cdb
vhdl xiyiji/simulate/db/simulate.sgdiff.hdb
vhdl xiyiji/simulate/db/simulate.sim.cvwf
vhdl xiyiji/simulate/db/simulate.sim.hdb
vhdl xiyiji/simulate/db/simulate.sim.qmsg
vhdl xiyiji/simulate/db/simulate.sim.rdb
vhdl xiyiji/simulate/db/simulate.sld_design_entry.sci
vhdl xiyiji/simulate/db/simulate.sld_design_entry_dsc.sci
vhdl xiyiji/simulate/db/simulate.syn_hier_info
vhdl xiyiji/simulate/db/simulate.tan.qmsg
vhdl xiyiji/simulate/db/simulate.tis_db_list.ddb
vhdl xiyiji/simulate/db/simulate.tmw_info
vhdl xiyiji/simulate/db/wed.wsf
vhdl xiyiji/simulate/incremental_db/compiled_partitions/simulate.root_partition.map.kpt
vhdl xiyiji/simulate/incremental_db/README
vhdl xiyiji/simulate/modein.bsf
vhdl xiyiji/simulate/modein.vhd
vhdl xiyiji/simulate/set.bsf
vhdl xiyiji/simulate/set.vhd
vhdl xiyiji/simulate/simulate.asm.rpt
vhdl xiyiji/simulate/simulate.bdf
vhdl xiyiji/simulate/simulate.done
vhdl xiyiji/simulate/simulate.fit.rpt
vhdl xiyiji/simulate/simulate.fit.smsg
vhdl xiyiji/simulate/simulate.fit.summary
vhdl xiyiji/simulate/simulate.flow.rpt
vhdl xiyiji/simulate/simulate.map.rpt
vhdl xiyiji/simulate/simulate.map.summary
vhdl xiyiji/simulate/simulate.pin
vhdl xiyiji/simulate/simulate.pof
vhdl xiyiji/simulate/simulate.qpf
vhdl xiyiji/simulate/simulate.qsf
vhdl xiyiji/simulate/simulate.qws
vhdl xiyiji/simulate/simulate.sim.rpt
vhdl xiyiji/simulate/simulate.tan.rpt
vhdl xiyiji/simulate/simulate.tan.summary
vhdl xiyiji/simulate/simulate.vwf
vhdl xiyiji/wash/count_time.vhd
vhdl xiyiji/wash/db/prev_cmp_wash.asm.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.fit.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.map.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.qmsg
vhdl xiyiji/wash/db/prev_cmp_wash.tan.qmsg
vhdl xiyiji/wash/db/wash.(0).cnf.cdb
vhdl xiyiji/wash/db/wash.(0).cnf.hdb
vhdl xiyiji/wash/db/wash.(1).cnf.cdb
vhdl xiyiji/wash/db/wash.(1).cnf.hdb
vhdl xiyiji/wash/db/wash.(2).cnf.cdb
vhdl xiyiji/wash/db/wash.(2).cnf.hdb
vhdl xiyiji/wash/db/wash.(3).cnf.cdb
vhdl xiyiji/wash/db/wash.(3).cnf.hdb
vhdl xiyiji/wash/db/wash.(4).cnf.cdb
vhdl xiyiji/wash/db/wash.(4).cnf.hdb
vhdl xiyiji/wash/db/wash.asm.qmsg
vhdl xiyiji/wash/db/wash.asm_labs.ddb
vhdl xiyiji/wash/db/wash.cbx.xml
vhdl xiyiji/wash/db/wash.cmp.cdb
vhdl xiyiji/wash/db/wash.cmp.hdb
vhdl xiyiji/wash/db/wash.cmp.logdb
vhdl xiyiji/wash/db/wash.cmp.rdb
vhdl xiyiji/wash/db/wash.cmp.tdb
vhdl xiyiji/wash/db/wash.cmp0.ddb
vhdl xiyiji/wash/db/wash.dbp
vhdl xiyiji/wash/db/wash.db_info
vhdl xiyiji/wash/db/wash.eco.cdb
vhdl xiyiji/wash/db/wash.fit.qmsg
vhdl xiyiji/wash/db/wash.hier_info
vhdl xiyiji/wash/db/wash.hif
vhdl xiyiji/wash/db/wash.map.cdb
vhdl xiyiji/wash/db/wash.map.hdb
vhdl xiyiji/wash/db/wash.map.logdb
vhdl xiyiji/wash/db/wash.map.qmsg
vhdl xiyiji/wash/db/wash.pre_map.cdb
vhdl xiyiji/wash/db/wash.pre_map.hdb
vhdl xiyiji/wash/db/wash.psp
vhdl xiyiji/wash/db/wash.pss
vhdl xiyiji/wash/db/wash.rtlv.hdb
vhdl xiyiji/wash/db/wash.rtlv_sg.cdb
vhdl xiyiji/wash/db/wash.rtlv_sg_swap.cdb
vhdl xiyiji/wash/db/wash.sgdiff.cdb
vhdl xiyiji/wash/db/wash.sgdiff.hdb
vhdl xiyiji/wash/db/wash.signalprobe.cdb
vhdl xiyiji/wash/db/wash.sld_design_entry.sci
vhdl xiyiji/wash/db/wash.sld_design_entry_dsc.sci
vhdl xiyiji/wash/db/wash.syn_hier_info
vhdl xiyiji/wash/db
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