文件名称:PLL_prj
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- 上传时间:2012-11-16
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文件大小:31.9kb
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已下载:0次
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介绍说明--下载内容来自于网络,使用问题请自行百度
对锁相环频率综合器进行仿真计算,以优化环路参数。-PLL frequency synthesizer for the simulation to optimize the loop parameters.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
PLL_prj/de_sim.cfg
PLL_prj/de_sim.cfg.old
PLL_prj/hpeesofsim.cfg
PLL_prj/hpeesofsim.cfg.old
PLL_prj/layout.prf
PLL_prj/mil_layout.prf
PLL_prj/mil_schematic.prf
PLL_prj/momServer.log
PLL_prj/netlist.log
PLL_prj/networks/DPFDCP.ael
PLL_prj/networks/DPFDCP.atf
PLL_prj/networks/DPFDCP.dsn
PLL_prj/networks/DVcoDivideByN.ael
PLL_prj/networks/DVcoDivideByN.atf
PLL_prj/networks/DVcoDivideByN.bak
PLL_prj/networks/DVcoDivideByN.dsn
PLL_prj/networks/PLL.ael
PLL_prj/networks/PLL.atf
PLL_prj/networks/PLL.bak
PLL_prj/networks/PLL.dsn
PLL_prj/networks/SigmaDelta4order.ael
PLL_prj/networks/SigmaDelta4order.atf
PLL_prj/networks/SigmaDelta4order.bak
PLL_prj/networks/SigmaDelta4order.dsn
PLL_prj/networks/untitled1.bak
PLL_prj/project.ads
PLL_prj/save_project_state.ael
PLL_prj/save_project_state.bak
PLL_prj/schematic.prf
PLL_prj/veriloga/DPFDCP.va
PLL_prj/veriloga/DVcoDivideByN.va
PLL_prj/veriloga/SigmaDelta4order.va
PLL_prj/data
PLL_prj/mom_dsn
PLL_prj/networks
PLL_prj/synthesis
PLL_prj/verification
PLL_prj/veriloga
PLL_prj
PLL_prj/de_sim.cfg.old
PLL_prj/hpeesofsim.cfg
PLL_prj/hpeesofsim.cfg.old
PLL_prj/layout.prf
PLL_prj/mil_layout.prf
PLL_prj/mil_schematic.prf
PLL_prj/momServer.log
PLL_prj/netlist.log
PLL_prj/networks/DPFDCP.ael
PLL_prj/networks/DPFDCP.atf
PLL_prj/networks/DPFDCP.dsn
PLL_prj/networks/DVcoDivideByN.ael
PLL_prj/networks/DVcoDivideByN.atf
PLL_prj/networks/DVcoDivideByN.bak
PLL_prj/networks/DVcoDivideByN.dsn
PLL_prj/networks/PLL.ael
PLL_prj/networks/PLL.atf
PLL_prj/networks/PLL.bak
PLL_prj/networks/PLL.dsn
PLL_prj/networks/SigmaDelta4order.ael
PLL_prj/networks/SigmaDelta4order.atf
PLL_prj/networks/SigmaDelta4order.bak
PLL_prj/networks/SigmaDelta4order.dsn
PLL_prj/networks/untitled1.bak
PLL_prj/project.ads
PLL_prj/save_project_state.ael
PLL_prj/save_project_state.bak
PLL_prj/schematic.prf
PLL_prj/veriloga/DPFDCP.va
PLL_prj/veriloga/DVcoDivideByN.va
PLL_prj/veriloga/SigmaDelta4order.va
PLL_prj/data
PLL_prj/mom_dsn
PLL_prj/networks
PLL_prj/synthesis
PLL_prj/verification
PLL_prj/veriloga
PLL_prj
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