文件名称:SingleLoopSDM_prj
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- 上传时间:2012-11-16
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文件大小:834.4kb
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对频率综合器中的小数分频器进行优化配置,减小参考杂散。-Of the fractional frequency divider in the synthesizer to optimize the configuration, reducing the reference spur.
相关搜索: single loop SDM
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下载文件列表
SingleLoopSDM_prj/data/testinteger.ds
SingleLoopSDM_prj/data/testSDM.ds
SingleLoopSDM_prj/data/__simdata010728.ds
SingleLoopSDM_prj/data/__simdata032098.ds
SingleLoopSDM_prj/data/__simdata113736.ds
SingleLoopSDM_prj/de_sim.cfg
SingleLoopSDM_prj/de_sim.cfg.old
SingleLoopSDM_prj/hpeesofsim.cfg
SingleLoopSDM_prj/hpeesofsim.cfg.old
SingleLoopSDM_prj/layout.prf
SingleLoopSDM_prj/mil_layout.prf
SingleLoopSDM_prj/mil_schematic.prf
SingleLoopSDM_prj/momServer.log
SingleLoopSDM_prj/netlist.log
SingleLoopSDM_prj/networks/SigmaDelta3order.ael
SingleLoopSDM_prj/networks/SigmaDelta3order.atf
SingleLoopSDM_prj/networks/SigmaDelta3order.bak
SingleLoopSDM_prj/networks/SigmaDelta3order.dsn
SingleLoopSDM_prj/networks/SigmaDelta4order.ael
SingleLoopSDM_prj/networks/SigmaDelta4order.atf
SingleLoopSDM_prj/networks/SigmaDelta4order.bak
SingleLoopSDM_prj/networks/SigmaDelta4order.dsn
SingleLoopSDM_prj/networks/test3order.ael
SingleLoopSDM_prj/networks/test3order.atf
SingleLoopSDM_prj/networks/test3order.bak
SingleLoopSDM_prj/networks/test3order.dsn
SingleLoopSDM_prj/networks/test4order.ael
SingleLoopSDM_prj/networks/test4order.dsn
SingleLoopSDM_prj/point.txt
SingleLoopSDM_prj/point1.txt
SingleLoopSDM_prj/project.ads
SingleLoopSDM_prj/save_project_state.ael
SingleLoopSDM_prj/save_project_state.bak
SingleLoopSDM_prj/schematic.prf
SingleLoopSDM_prj/test3order.dds
SingleLoopSDM_prj/test4order.dds
SingleLoopSDM_prj/veriloga/SigmaDelta3order.va
SingleLoopSDM_prj/veriloga/SigmaDelta4order.va
SingleLoopSDM_prj/data
SingleLoopSDM_prj/mom_dsn
SingleLoopSDM_prj/networks
SingleLoopSDM_prj/synthesis
SingleLoopSDM_prj/verification
SingleLoopSDM_prj/veriloga
SingleLoopSDM_prj
SingleLoopSDM_prj/data/testSDM.ds
SingleLoopSDM_prj/data/__simdata010728.ds
SingleLoopSDM_prj/data/__simdata032098.ds
SingleLoopSDM_prj/data/__simdata113736.ds
SingleLoopSDM_prj/de_sim.cfg
SingleLoopSDM_prj/de_sim.cfg.old
SingleLoopSDM_prj/hpeesofsim.cfg
SingleLoopSDM_prj/hpeesofsim.cfg.old
SingleLoopSDM_prj/layout.prf
SingleLoopSDM_prj/mil_layout.prf
SingleLoopSDM_prj/mil_schematic.prf
SingleLoopSDM_prj/momServer.log
SingleLoopSDM_prj/netlist.log
SingleLoopSDM_prj/networks/SigmaDelta3order.ael
SingleLoopSDM_prj/networks/SigmaDelta3order.atf
SingleLoopSDM_prj/networks/SigmaDelta3order.bak
SingleLoopSDM_prj/networks/SigmaDelta3order.dsn
SingleLoopSDM_prj/networks/SigmaDelta4order.ael
SingleLoopSDM_prj/networks/SigmaDelta4order.atf
SingleLoopSDM_prj/networks/SigmaDelta4order.bak
SingleLoopSDM_prj/networks/SigmaDelta4order.dsn
SingleLoopSDM_prj/networks/test3order.ael
SingleLoopSDM_prj/networks/test3order.atf
SingleLoopSDM_prj/networks/test3order.bak
SingleLoopSDM_prj/networks/test3order.dsn
SingleLoopSDM_prj/networks/test4order.ael
SingleLoopSDM_prj/networks/test4order.dsn
SingleLoopSDM_prj/point.txt
SingleLoopSDM_prj/point1.txt
SingleLoopSDM_prj/project.ads
SingleLoopSDM_prj/save_project_state.ael
SingleLoopSDM_prj/save_project_state.bak
SingleLoopSDM_prj/schematic.prf
SingleLoopSDM_prj/test3order.dds
SingleLoopSDM_prj/test4order.dds
SingleLoopSDM_prj/veriloga/SigmaDelta3order.va
SingleLoopSDM_prj/veriloga/SigmaDelta4order.va
SingleLoopSDM_prj/data
SingleLoopSDM_prj/mom_dsn
SingleLoopSDM_prj/networks
SingleLoopSDM_prj/synthesis
SingleLoopSDM_prj/verification
SingleLoopSDM_prj/veriloga
SingleLoopSDM_prj
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