4位乘法器 vhdl

library IEEE

use IEEE.std_logic_1164.all



entity one_bit_adder is

　　port (

　　　　A: in STD_LOGIC

　　　　B: in STD_LOGIC

　　　　C_in: in STD_LOGIC

　　　　S: out STD_LOGIC

　　　　C_out: out STD_LOGIC

　　)

end one_bit_adder -4-bit multiplier vhdl library IEEE　use IEEE.std_logic_1164.all　entity one_bit_adder is port (A: in STD_LOGIC　B: in STD_LOGIC　C_in: in STD_LOGIC　S: out STD_LOGIC　C_out: out STD_LOGIC)　end one_bit_adder