一个VHDL实现的测频计

LIBRARY ieee

USE ieee.std_logic_1164.all

USE ieee.std_logic_arith.all

USE ieee.std_logic_unsigned.all



ENTITY freq IS

PORT( Fsignal : IN std_logic

-- Rst : IN std_logic

Gate : IN std_logic

Ready : OUT std_logic

Data_out : OUT std_logic_vector(31 downto 0)

overflow : OUT std_logic

)

END freq

-A VHDL implementation of frequency meter LIBRARY ieee　USE ieee.std_logic_1164.all　USE ieee.std_logic_arith.all　USE ieee.std_logic_unsigned.all　ENTITY freq IS PORT (Fsignal: IN std_logic - Rst: IN std_logic　Gate: IN std_logic　Ready: OUT std_logic　Data_out: OUT std_logic_vector (31 downto 0)　overflow: OUT std_logic)　END freq