文件名称:SG_FPGA
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- 上传时间：2012-11-16
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文件大小：1.05mb
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2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the device schematic FPGA, VHDL code with the descr iption of the main modules, including the PLL, phase accumulator, sine lookup table algorithm and the waveform can be realized 0.005Hz ~ 20MHz multi-waveform signal generator, the frequency step value of 0.005, then the output rate of 100MSPS DAC- AD9762
相关搜索： AD9762
VHDL 函数信号发生器
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SG_FPGA/add.bsf
SG_FPGA/add.inc
SG_FPGA/add.vhd
SG_FPGA/ADD1.bsf
SG_FPGA/ADD1.inc
SG_FPGA/ADD1.vhd
SG_FPGA/cmp.bsf
SG_FPGA/cmp.inc
SG_FPGA/cmp.vhd
SG_FPGA/db/accum_v0e.tdf
SG_FPGA/db/add_sub_6fg.tdf
SG_FPGA/db/cmpr_09i.tdf
SG_FPGA/db/cmpr_99i.tdf
SG_FPGA/db/cntr_peh.tdf
SG_FPGA/db/decode_q0f.tdf
SG_FPGA/db/mux_2td.tdf
SG_FPGA/db/mux_5td.tdf
SG_FPGA/db/mux_dee.tdf
SG_FPGA/db/signal.db_info
SG_FPGA/db/signal.eco.cdb
SG_FPGA/db/signal.sld_design_entry.sci
SG_FPGA/decode16.bsf
SG_FPGA/decode16.inc
SG_FPGA/decode16.vhd
SG_FPGA/mux3.bsf
SG_FPGA/mux3.inc
SG_FPGA/mux3.vhd
SG_FPGA/or.bsf
SG_FPGA/or.inc
SG_FPGA/or.vhd
SG_FPGA/PLL1.bsf
SG_FPGA/PLL1.inc
SG_FPGA/PLL1.ppf
SG_FPGA/PLL1.vhd
SG_FPGA/PLL1_wave0.jpg
SG_FPGA/PLL1_waveforms.html
SG_FPGA/signal.asm.rpt
SG_FPGA/signal.bdf
SG_FPGA/signal.cdf
SG_FPGA/signal.done
SG_FPGA/signal.dpf
SG_FPGA/signal.fit.rpt
SG_FPGA/signal.fit.smsg
SG_FPGA/signal.fit.summary
SG_FPGA/signal.flow.rpt
SG_FPGA/signal.map.rpt
SG_FPGA/signal.map.summary
SG_FPGA/signal.pin
SG_FPGA/signal.pof
SG_FPGA/signal.qpf
SG_FPGA/signal.qsf
SG_FPGA/signal.qws
SG_FPGA/signal.sof
SG_FPGA/signal.tan.rpt
SG_FPGA/signal.tan.summary
SG_FPGA/signal_assignment_defaults.qdf
SG_FPGA/X.rar
SG_FPGA/db
SG_FPGA
SG_FPGA/add.inc
SG_FPGA/add.vhd
SG_FPGA/ADD1.bsf
SG_FPGA/ADD1.inc
SG_FPGA/ADD1.vhd
SG_FPGA/cmp.bsf
SG_FPGA/cmp.inc
SG_FPGA/cmp.vhd
SG_FPGA/db/accum_v0e.tdf
SG_FPGA/db/add_sub_6fg.tdf
SG_FPGA/db/cmpr_09i.tdf
SG_FPGA/db/cmpr_99i.tdf
SG_FPGA/db/cntr_peh.tdf
SG_FPGA/db/decode_q0f.tdf
SG_FPGA/db/mux_2td.tdf
SG_FPGA/db/mux_5td.tdf
SG_FPGA/db/mux_dee.tdf
SG_FPGA/db/signal.db_info
SG_FPGA/db/signal.eco.cdb
SG_FPGA/db/signal.sld_design_entry.sci
SG_FPGA/decode16.bsf
SG_FPGA/decode16.inc
SG_FPGA/decode16.vhd
SG_FPGA/mux3.bsf
SG_FPGA/mux3.inc
SG_FPGA/mux3.vhd
SG_FPGA/or.bsf
SG_FPGA/or.inc
SG_FPGA/or.vhd
SG_FPGA/PLL1.bsf
SG_FPGA/PLL1.inc
SG_FPGA/PLL1.ppf
SG_FPGA/PLL1.vhd
SG_FPGA/PLL1_wave0.jpg
SG_FPGA/PLL1_waveforms.html
SG_FPGA/signal.asm.rpt
SG_FPGA/signal.bdf
SG_FPGA/signal.cdf
SG_FPGA/signal.done
SG_FPGA/signal.dpf
SG_FPGA/signal.fit.rpt
SG_FPGA/signal.fit.smsg
SG_FPGA/signal.fit.summary
SG_FPGA/signal.flow.rpt
SG_FPGA/signal.map.rpt
SG_FPGA/signal.map.summary
SG_FPGA/signal.pin
SG_FPGA/signal.pof
SG_FPGA/signal.qpf
SG_FPGA/signal.qsf
SG_FPGA/signal.qws
SG_FPGA/signal.sof
SG_FPGA/signal.tan.rpt
SG_FPGA/signal.tan.summary
SG_FPGA/signal_assignment_defaults.qdf
SG_FPGA/X.rar
SG_FPGA/db
SG_FPGA
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