文件名称:JPEG
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所属分类:
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- 上传时间:2012-11-16
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文件大小:184.09kb
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已下载:1次
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提 供 者:
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介绍说明--下载内容来自于网络,使用问题请自行百度
JPEG解码(Verilog)源码,详细,高效。-JPEG decoding (Verilog)
相关搜索: JPEG verilog
verilog jpeg
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下载文件列表
JPEG/fpga_jpeg/dct/dct.v
JPEG/fpga_jpeg/dct/dctu.v
JPEG/fpga_jpeg/dct/dctub.v
JPEG/fpga_jpeg/dct/dct_bench/bench_top.v
JPEG/fpga_jpeg/dct/dct_cos_table.v
JPEG/fpga_jpeg/dct/dct_mac.v
JPEG/fpga_jpeg/dct/dct_syn.v
JPEG/fpga_jpeg/dct/fdct.v
JPEG/fpga_jpeg/dct/huffman/bench/bench_top.v
JPEG/fpga_jpeg/dct/huffman/bench/generic_dpram.v
JPEG/fpga_jpeg/dct/huffman/bench/generic_fifo_lfsr.v
JPEG/fpga_jpeg/dct/huffman/bench/lfsr.v
JPEG/fpga_jpeg/dct/huffman/bench/timescale.v
JPEG/fpga_jpeg/dct/huffman/huffman_dec.v
JPEG/fpga_jpeg/dct/huffman/huffman_dec.v.bak
JPEG/fpga_jpeg/dct/huffman/huffman_enc.v
JPEG/fpga_jpeg/dct/huffman/huffman_tables.v
JPEG/fpga_jpeg/dct/huffman_tables.v
JPEG/fpga_jpeg/dct/rtl_sim/Makefile.txt
JPEG/fpga_jpeg/dct/timescale.v
JPEG/fpga_jpeg/dct/zigzag.v
JPEG/fpga_jpeg/jpeg/bench_top/jpeg_encoder.v
JPEG/fpga_jpeg/jpeg/dct.v
JPEG/fpga_jpeg/jpeg/dctu.v
JPEG/fpga_jpeg/jpeg/dctu.v.bak
JPEG/fpga_jpeg/jpeg/dctub.v
JPEG/fpga_jpeg/jpeg/dct_cos_table.v
JPEG/fpga_jpeg/jpeg/dct_mac.v
JPEG/fpga_jpeg/jpeg/dct_syn.v
JPEG/fpga_jpeg/jpeg/div_su.v
JPEG/fpga_jpeg/jpeg/div_uu.v
JPEG/fpga_jpeg/jpeg/fdct.v
JPEG/fpga_jpeg/jpeg/huffman_enc.v
JPEG/fpga_jpeg/jpeg/huffman_enc.v.bak
JPEG/fpga_jpeg/jpeg/huffman_tables.v
JPEG/fpga_jpeg/jpeg/jpeg_encoder.v
JPEG/fpga_jpeg/jpeg/jpeg_encoder.v.bak
JPEG/fpga_jpeg/jpeg/jpeg_qnr.v
JPEG/fpga_jpeg/jpeg/jpeg_rle.v
JPEG/fpga_jpeg/jpeg/jpeg_rle1.v
JPEG/fpga_jpeg/jpeg/jpeg_rzs.v
JPEG/fpga_jpeg/jpeg/sim/cds.lib
JPEG/fpga_jpeg/jpeg/sim/hdl.var
JPEG/fpga_jpeg/jpeg/sim/Makefile.txt
JPEG/fpga_jpeg/jpeg/zigzag.v
JPEG/fpga_jpeg/qnr/attic/div.v
JPEG/fpga_jpeg/qnr/attic/div_us.v
JPEG/fpga_jpeg/qnr/attic/ro_cnt.v
JPEG/fpga_jpeg/qnr/attic/ud_cnt.v
JPEG/fpga_jpeg/qnr/bench/bench_div_top.v
JPEG/fpga_jpeg/qnr/bench/bench_qnr_top.v
JPEG/fpga_jpeg/qnr/bench/timescale.v
JPEG/fpga_jpeg/qnr/div_su.v
JPEG/fpga_jpeg/qnr/div_uu.v
JPEG/fpga_jpeg/qnr/jpeg_qnr.v
JPEG/fpga_jpeg/rgb2ycrcb/modelsim.ini
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb/_info
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb.mpf
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb.v
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb_testbench.v
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb_webAddress.txt
JPEG/fpga_jpeg/rgb2ycrcb/tcl_stacktrace.txt
JPEG/fpga_jpeg/rgb2ycrcb/transcript
JPEG/fpga_jpeg/rgb2ycrcb/work/_info
JPEG/fpga_jpeg/run_length_coding/attic/jpeg_rle2.v
JPEG/fpga_jpeg/run_length_coding/bench/bench.v
JPEG/fpga_jpeg/run_length_coding/jpeg_rle.v
JPEG/fpga_jpeg/run_length_coding/jpeg_rle1.v
JPEG/fpga_jpeg/run_length_coding/jpeg_rzs.v
JPEG/fpga_jpeg/dct/huffman/bench
JPEG/fpga_jpeg/dct/dct_bench
JPEG/fpga_jpeg/dct/huffman
JPEG/fpga_jpeg/dct/rtl_sim
JPEG/fpga_jpeg/jpeg/bench_top
JPEG/fpga_jpeg/jpeg/sim
JPEG/fpga_jpeg/qnr/attic
JPEG/fpga_jpeg/qnr/bench
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb
JPEG/fpga_jpeg/rgb2ycrcb/work
JPEG/fpga_jpeg/run_length_coding/attic
JPEG/fpga_jpeg/run_length_coding/bench
JPEG/fpga_jpeg/dct
JPEG/fpga_jpeg/jpeg
JPEG/fpga_jpeg/qnr
JPEG/fpga_jpeg/rgb2ycrcb
JPEG/fpga_jpeg/run_length_coding
JPEG/fpga_jpeg
JPEG
JPEG/fpga_jpeg/dct/dctu.v
JPEG/fpga_jpeg/dct/dctub.v
JPEG/fpga_jpeg/dct/dct_bench/bench_top.v
JPEG/fpga_jpeg/dct/dct_cos_table.v
JPEG/fpga_jpeg/dct/dct_mac.v
JPEG/fpga_jpeg/dct/dct_syn.v
JPEG/fpga_jpeg/dct/fdct.v
JPEG/fpga_jpeg/dct/huffman/bench/bench_top.v
JPEG/fpga_jpeg/dct/huffman/bench/generic_dpram.v
JPEG/fpga_jpeg/dct/huffman/bench/generic_fifo_lfsr.v
JPEG/fpga_jpeg/dct/huffman/bench/lfsr.v
JPEG/fpga_jpeg/dct/huffman/bench/timescale.v
JPEG/fpga_jpeg/dct/huffman/huffman_dec.v
JPEG/fpga_jpeg/dct/huffman/huffman_dec.v.bak
JPEG/fpga_jpeg/dct/huffman/huffman_enc.v
JPEG/fpga_jpeg/dct/huffman/huffman_tables.v
JPEG/fpga_jpeg/dct/huffman_tables.v
JPEG/fpga_jpeg/dct/rtl_sim/Makefile.txt
JPEG/fpga_jpeg/dct/timescale.v
JPEG/fpga_jpeg/dct/zigzag.v
JPEG/fpga_jpeg/jpeg/bench_top/jpeg_encoder.v
JPEG/fpga_jpeg/jpeg/dct.v
JPEG/fpga_jpeg/jpeg/dctu.v
JPEG/fpga_jpeg/jpeg/dctu.v.bak
JPEG/fpga_jpeg/jpeg/dctub.v
JPEG/fpga_jpeg/jpeg/dct_cos_table.v
JPEG/fpga_jpeg/jpeg/dct_mac.v
JPEG/fpga_jpeg/jpeg/dct_syn.v
JPEG/fpga_jpeg/jpeg/div_su.v
JPEG/fpga_jpeg/jpeg/div_uu.v
JPEG/fpga_jpeg/jpeg/fdct.v
JPEG/fpga_jpeg/jpeg/huffman_enc.v
JPEG/fpga_jpeg/jpeg/huffman_enc.v.bak
JPEG/fpga_jpeg/jpeg/huffman_tables.v
JPEG/fpga_jpeg/jpeg/jpeg_encoder.v
JPEG/fpga_jpeg/jpeg/jpeg_encoder.v.bak
JPEG/fpga_jpeg/jpeg/jpeg_qnr.v
JPEG/fpga_jpeg/jpeg/jpeg_rle.v
JPEG/fpga_jpeg/jpeg/jpeg_rle1.v
JPEG/fpga_jpeg/jpeg/jpeg_rzs.v
JPEG/fpga_jpeg/jpeg/sim/cds.lib
JPEG/fpga_jpeg/jpeg/sim/hdl.var
JPEG/fpga_jpeg/jpeg/sim/Makefile.txt
JPEG/fpga_jpeg/jpeg/zigzag.v
JPEG/fpga_jpeg/qnr/attic/div.v
JPEG/fpga_jpeg/qnr/attic/div_us.v
JPEG/fpga_jpeg/qnr/attic/ro_cnt.v
JPEG/fpga_jpeg/qnr/attic/ud_cnt.v
JPEG/fpga_jpeg/qnr/bench/bench_div_top.v
JPEG/fpga_jpeg/qnr/bench/bench_qnr_top.v
JPEG/fpga_jpeg/qnr/bench/timescale.v
JPEG/fpga_jpeg/qnr/div_su.v
JPEG/fpga_jpeg/qnr/div_uu.v
JPEG/fpga_jpeg/qnr/jpeg_qnr.v
JPEG/fpga_jpeg/rgb2ycrcb/modelsim.ini
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb/_info
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb.mpf
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb.v
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb_testbench.v
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb_webAddress.txt
JPEG/fpga_jpeg/rgb2ycrcb/tcl_stacktrace.txt
JPEG/fpga_jpeg/rgb2ycrcb/transcript
JPEG/fpga_jpeg/rgb2ycrcb/work/_info
JPEG/fpga_jpeg/run_length_coding/attic/jpeg_rle2.v
JPEG/fpga_jpeg/run_length_coding/bench/bench.v
JPEG/fpga_jpeg/run_length_coding/jpeg_rle.v
JPEG/fpga_jpeg/run_length_coding/jpeg_rle1.v
JPEG/fpga_jpeg/run_length_coding/jpeg_rzs.v
JPEG/fpga_jpeg/dct/huffman/bench
JPEG/fpga_jpeg/dct/dct_bench
JPEG/fpga_jpeg/dct/huffman
JPEG/fpga_jpeg/dct/rtl_sim
JPEG/fpga_jpeg/jpeg/bench_top
JPEG/fpga_jpeg/jpeg/sim
JPEG/fpga_jpeg/qnr/attic
JPEG/fpga_jpeg/qnr/bench
JPEG/fpga_jpeg/rgb2ycrcb/rgb2ycrcb
JPEG/fpga_jpeg/rgb2ycrcb/work
JPEG/fpga_jpeg/run_length_coding/attic
JPEG/fpga_jpeg/run_length_coding/bench
JPEG/fpga_jpeg/dct
JPEG/fpga_jpeg/jpeg
JPEG/fpga_jpeg/qnr
JPEG/fpga_jpeg/rgb2ycrcb
JPEG/fpga_jpeg/run_length_coding
JPEG/fpga_jpeg
JPEG
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