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文件名称:nios2net

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [MacOS] [C/C++] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.73mb
  • 已下载：
    0次
  • 提 供 者：
    eins****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

nios2实习的网络通讯，基于dm9000a芯片。在de2-70开发版上实习，内部附有所以源码，nios的源码放在software文件夹下面。-nios2 internship network communications based on dm9000a chip. Version of the de2-70 on the practical development of the internal source with it, nios software folder on the source below.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

nios2net1/.sopc_builder/install.ptf
nios2net1/.sopc_builder/install2.ptf
nios2net1/.sopc_builder/preferences.xml
nios2net1/Altera_UP_Avalon_PS2.v
nios2net1/Altera_UP_PS2.v
nios2net1/Altera_UP_PS2_Command_Out.v
nios2net1/Altera_UP_PS2_Data_In.v
nios2net1/altpllpll.bsf
nios2net1/altpllpll.ppf
nios2net1/altpllpll.v
nios2net1/AUDIO.v
nios2net1/clock_0.v
nios2net1/clock_1.v
nios2net1/cpu.ocp
nios2net1/cpu.v
nios2net1/cpu_bht_ram.mif
nios2net1/cpu_dc_tag_ram.mif
nios2net1/cpu_ic_tag_ram.mif
nios2net1/cpu_jtag_debug_module.v
nios2net1/cpu_jtag_debug_module_wrapper.v
nios2net1/cpu_mult_cell.v
nios2net1/cpu_ociram_default_contents.mif
nios2net1/cpu_rf_ram_a.mif
nios2net1/cpu_rf_ram_b.mif
nios2net1/cpu_test_bench.v
nios2net1/DE2_70_NET.asm.rpt
nios2net1/DE2_70_NET.cdf
nios2net1/DE2_70_NET.done
nios2net1/DE2_70_NET.dpf
nios2net1/DE2_70_NET.fit.rpt
nios2net1/DE2_70_NET.fit.smsg
nios2net1/DE2_70_NET.fit.summary
nios2net1/DE2_70_NET.flow.rpt
nios2net1/DE2_70_NET.jdi
nios2net1/DE2_70_NET.map.rpt
nios2net1/DE2_70_NET.map.smsg
nios2net1/DE2_70_NET.map.summary
nios2net1/DE2_70_NET.pin
nios2net1/DE2_70_NET.pof
nios2net1/DE2_70_NET.qpf
nios2net1/DE2_70_NET.qsf
nios2net1/DE2_70_NET.qsf.bak
nios2net1/DE2_70_NET.qws
nios2net1/DE2_70_NET.sof
nios2net1/DE2_70_NET.tan.rpt
nios2net1/DE2_70_NET.tan.summary
nios2net1/DE2_70_NET.v
nios2net1/DE2_70_NET.v.bak
nios2net1/DE2_70_NET_assignment_defaults.qdf
nios2net1/DE2_70_NET_SOPC.sop
nios2net1/DE2_70_SOPC.bsf
nios2net1/DE2_70_SOPC.ptf
nios2net1/DE2_70_SOPC.ptf.bak
nios2net1/DE2_70_SOPC.ptf.pre_generation_ptf
nios2net1/DE2_70_SOPC.qip
nios2net1/DE2_70_SOPC.sopc
nios2net1/DE2_70_SOPC.v
nios2net1/DE2_70_SOPC_generation_script
nios2net1/DE2_70_SOPC_log.txt
nios2net1/DE2_70_SOPC_setup_quartus.tcl
nios2net1/DE2_70_SOPC_sim/atail-f.pl
nios2net1/DE2_70_SOPC_sim/dummy_file
nios2net1/DE2_70_SOPC_sim/jtag_uart_input_mutex.dat
nios2net1/DE2_70_SOPC_sim/jtag_uart_input_stream.dat
nios2net1/DE2_70_SOPC_sim/jtag_uart_output_stream.dat
nios2net1/DE2_70_SOPC_sim/uart_input_data_mutex.dat
nios2net1/DE2_70_SOPC_sim/uart_input_data_stream.dat
nios2net1/DE2_70_SOPC_sim/uart_log_module.txt
nios2net1/DM9000A.v
nios2net1/DM9000A_IF_inst.v
nios2net1/i2c_sclk.v
nios2net1/i2c_sdat.v
nios2net1/incremental_db/README
nios2net1/IP/TERASIC_AUDIO/hdl/AUDIO_ADC.v
nios2net1/IP/TERASIC_AUDIO/hdl/AUDIO_DAC.v
nios2net1/IP/TERASIC_AUDIO/hdl/audio_fifo.v
nios2net1/IP/TERASIC_AUDIO/hdl/audio_fifo_wave0.jpg
nios2net1/IP/TERASIC_AUDIO/hdl/audio_fifo_wave1.jpg
nios2net1/IP/TERASIC_AUDIO/hdl/audio_fifo_waveforms.html
nios2net1/IP/TERASIC_AUDIO/hdl/AUDIO_IF.v
nios2net1/IP/TERASIC_AUDIO/hdl/AUDIO_IF.v.bak
nios2net1/IP/TERASIC_AUDIO/hdl/AUDIO_IF_hw.tcl
nios2net1/IP/TERASIC_AUDIO/software/AUDIO.c
nios2net1/IP/TERASIC_AUDIO/software/AUDIO.h
nios2net1/IP/TERASIC_AUDIO/software/AUDIO_REG.h
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/Binary_VGA_Control_IF_hw.tcl
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/Binary_VGA_Control_IF_hw.tcl~
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/Img_DATA.hex
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/Img_RAM.v
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_Controller.v
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v.bak
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_OSD_RAM.v
nios2net1/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_Param.h
nios2net1/IP/TERASIC_DM9000A/hdl/DM9000A_IF.v
nios2net1/IP/TERASIC_DM9000A/hdl/DM9000A_IF_hw.tcl
nios2net1/IP/TERASIC_DM9000A/hdl/DM9000A_IF_hw.tcl~
nios2net1/IP/TERASIC_DM9000A/software/DM9000A.C
nios2net1/IP/TERASIC_DM9000A/software/DM9000A.H
nios2net1/IP/TERASIC_ISP1362/hdl/ISP1362_IF.v
nios2net1/IP/TERASIC_ISP1362/hdl/ISP1362_IF_hw.tcl
nios2net1/IP/TERASIC_SEG7/hdl/SEG7_IF.v
nios2net1/IP/TERASIC_SEG7/hdl/SEG7_IF_hw.tcl
nios2net1/IP/TERASIC_SEG7/software/SEG7.c
nios2net1/IP/TERASIC_SEG7/software/SEG7.h
nios2net1/ISP1362.v
nios2net1/jtag_uart.v
nios2net1/lcd.v
nios2net1/onchip_mem.hex
nios2net1/onchip_mem.v
nios2net1/pio_button.v
nios2net1/pio_green_led.v
nios2net1/pio_red_led.v
nios2net1/pio_switch.v
nios2net1/pll.v
nios2net1/prev_cmp_DE2_70_NET.qmsg
nios2net1/ps2_keyboard.v
nios2net1/ps2_mouse.v
nios2net1/Reset_Delay.v
nios2net1/sdram_u1.v
nios2net1/sdram_u1_test_component.v
nios2net1/sdram_u2.v
nios2net1/sdram_u2_test_component.v
nios2net1/sd_clk.v
nios2net1/sd_cmd.v
nios2net1/sd_dat.v
nios2net1/sd_dat3.v
nios2net1/SEG7.v
nios2net1/Software/altera.components/.cdtproject
nios2net1/Software/altera.components/.project
nios2net1/Software/altera.components/.settings/org.eclipse.cdt.core.prefs
nios2net1/Software/DE2_70_NET/.cdtbuild
nios2net1/Software/DE2_70_NET/.cdtproject
nios2net1/Software/DE2_70_NET/.project
nios2net1/Software/DE2_70_NET/.settings/org.eclipse.cdt.core.prefs
nios2net1/Software/DE2_70_NET/.settings/org.eclipse.cdt.managedbuilder.core.prefs
nios2net1/Software/DE2_70_NET/application.stf
nios2net1/Software/DE2_70_NET/basic_io.h
nios2net1/Software/DE2_70_NET/DE2_70_NET.c
nios2net1/Software/DE2_70_NET/Debug/cfi_flash.flash
nios2net1/Software/DE2_70_NET/Debug/DE2_70_NET.elf
nios2net1/Soft

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