文件名称:Single-port-RAM-
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- 上传时间:2012-11-16
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文件大小:1.07mb
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单口RAM带CLR信号的verilog程序。很详细的.-Single-port RAM with a CLR signal
相关搜索: single port ram
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RAM时序说明/
RAM时序说明/sys_ram_wave1.jpg
RAM时序说明/time0.JPG
RAM时序说明/time2.JPG
RAM时序说明/地址为高阻时的时序图.JPG
RAM时序说明/地址连续时的时序图.JPG
RAM时序说明/时序说明.txt
Source/
Source/db/
Source/db/altsyncram_f3c1.tdf
Source/db/altsyncram_t3d1.tdf
Source/db/logic_util_heursitic.dat
Source/db/prev_cmp_RAM.qmsg
Source/db/RAM.(0).cnf.cdb
Source/db/RAM.(0).cnf.hdb
Source/db/RAM.(1).cnf.cdb
Source/db/RAM.(1).cnf.hdb
Source/db/RAM.(2).cnf.cdb
Source/db/RAM.(2).cnf.hdb
Source/db/RAM.(3).cnf.cdb
Source/db/RAM.(3).cnf.hdb
Source/db/RAM.(4).cnf.cdb
Source/db/RAM.(4).cnf.hdb
Source/db/RAM.(5).cnf.cdb
Source/db/RAM.(5).cnf.hdb
Source/db/RAM.amm.cdb
Source/db/RAM.asm.qmsg
Source/db/RAM.asm.rdb
Source/db/RAM.cbx.xml
Source/db/RAM.cmp.bpm
Source/db/RAM.cmp.cdb
Source/db/RAM.cmp.hdb
Source/db/RAM.cmp.kpt
Source/db/RAM.cmp.logdb
Source/db/RAM.cmp.rdb
Source/db/RAM.cmp0.ddb
Source/db/RAM.cmp_merge.kpt
Source/db/RAM.db_info
Source/db/RAM.eda.qmsg
Source/db/RAM.fit.qmsg
Source/db/RAM.hier_info
Source/db/RAM.hif
Source/db/RAM.idb.cdb
Source/db/RAM.lpc.html
Source/db/RAM.lpc.rdb
Source/db/RAM.lpc.txt
Source/db/RAM.map.bpm
Source/db/RAM.map.cdb
Source/db/RAM.map.hdb
Source/db/RAM.map.kpt
Source/db/RAM.map.logdb
Source/db/RAM.map.qmsg
Source/db/RAM.map_bb.cdb
Source/db/RAM.map_bb.hdb
Source/db/RAM.map_bb.logdb
Source/db/RAM.pre_map.cdb
Source/db/RAM.pre_map.hdb
Source/db/RAM.rtlv.hdb
Source/db/RAM.rtlv_sg.cdb
Source/db/RAM.rtlv_sg_swap.cdb
Source/db/RAM.sgdiff.cdb
Source/db/RAM.sgdiff.hdb
Source/db/RAM.sld_design_entry.sci
Source/db/RAM.sld_design_entry_dsc.sci
Source/db/RAM.smart_action.txt
Source/db/RAM.sta.qmsg
Source/db/RAM.sta.rdb
Source/db/RAM.sta_cmp.8_slow.tdb
Source/db/RAM.syn_hier_info
Source/db/RAM.tis_db_list.ddb
Source/db/RAM.tmw_info
Source/greybox_tmp/
Source/greybox_tmp/cbx_args.txt
Source/incremental_db/
Source/incremental_db/compiled_partitions/
Source/incremental_db/compiled_partitions/RAM.db_info
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.cbp
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.cdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.dfp
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.hdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.kpt
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.logdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.rcfdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.re.rcfdb
Source/incremental_db/compiled_partitions/RAM.root_partition.map.cbp
Source/incremental_db/compiled_partitions/RAM.root_partition.map.cdb
Source/incremental_db/compiled_partitions/RAM.root_partition.map.dpi
Source/incremental_db/compiled_partitions/RAM.root_partition.map.hdb
Source/incremental_db/compiled_partitions/RAM.root_partition.map.kpt
Source/incremental_db/README
Source/RAM.asm.rpt
Source/RAM.done
Source/RAM.eda.rpt
Source/RAM.fit.rpt
Source/RAM.fit.summary
Source/RAM.flow.rpt
Source/RAM.map.rpt
Source/RAM.map.summary
Source/RAM.pin
Source/RAM.pof
Source/RAM.qpf
Source/RAM.qsf
Source/RAM.sof
Source/RAM.sta.rpt
Source/RAM.sta.summary
Source/RAM.v
Source/RAM.v.bak
Source/ram4.bsf
Source/RAM4.cmp
Source/RAM4.inc
Source/RAM4.qip
Source/RAM4.v
Source/RAM4_bb.v
Source/RAM4_inst.v
Source/simulation/
Source/simulation/modelsim/
Source/simulation/modelsim/a_ram_tb.v
Source/simulation/modelsim/a_ram_tb.v.bak
Source/simulation/modelsim/cyclone_atoms.v
Source/simulation/modelsim/RAM.sft
Source/simulation/modelsim/RAM.vo
Source/simulation/modelsim/RAM_modelsim.xrf
Source/simulation/modelsim/RAM_v.sdo
Source/simulation/modelsim/RAM_v.sdo_typ.csd
Source/simulation/modelsim/tb.cr.mti
Source/simulation/modelsim/tb.mpf
Source/simulation/modelsim/vsim.wlf
Source/simulation/modelsim/work/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/verilog.prw
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/verilog.psm
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/_primary.dat
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/_primary.dbs
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/_primary.vhd
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/verilog.prw
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/verilog.psm
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/_primary.dat
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/_primary.dbs
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/_primary.vhd
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.prw
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.psm
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@
RAM时序说明/sys_ram_wave1.jpg
RAM时序说明/time0.JPG
RAM时序说明/time2.JPG
RAM时序说明/地址为高阻时的时序图.JPG
RAM时序说明/地址连续时的时序图.JPG
RAM时序说明/时序说明.txt
Source/
Source/db/
Source/db/altsyncram_f3c1.tdf
Source/db/altsyncram_t3d1.tdf
Source/db/logic_util_heursitic.dat
Source/db/prev_cmp_RAM.qmsg
Source/db/RAM.(0).cnf.cdb
Source/db/RAM.(0).cnf.hdb
Source/db/RAM.(1).cnf.cdb
Source/db/RAM.(1).cnf.hdb
Source/db/RAM.(2).cnf.cdb
Source/db/RAM.(2).cnf.hdb
Source/db/RAM.(3).cnf.cdb
Source/db/RAM.(3).cnf.hdb
Source/db/RAM.(4).cnf.cdb
Source/db/RAM.(4).cnf.hdb
Source/db/RAM.(5).cnf.cdb
Source/db/RAM.(5).cnf.hdb
Source/db/RAM.amm.cdb
Source/db/RAM.asm.qmsg
Source/db/RAM.asm.rdb
Source/db/RAM.cbx.xml
Source/db/RAM.cmp.bpm
Source/db/RAM.cmp.cdb
Source/db/RAM.cmp.hdb
Source/db/RAM.cmp.kpt
Source/db/RAM.cmp.logdb
Source/db/RAM.cmp.rdb
Source/db/RAM.cmp0.ddb
Source/db/RAM.cmp_merge.kpt
Source/db/RAM.db_info
Source/db/RAM.eda.qmsg
Source/db/RAM.fit.qmsg
Source/db/RAM.hier_info
Source/db/RAM.hif
Source/db/RAM.idb.cdb
Source/db/RAM.lpc.html
Source/db/RAM.lpc.rdb
Source/db/RAM.lpc.txt
Source/db/RAM.map.bpm
Source/db/RAM.map.cdb
Source/db/RAM.map.hdb
Source/db/RAM.map.kpt
Source/db/RAM.map.logdb
Source/db/RAM.map.qmsg
Source/db/RAM.map_bb.cdb
Source/db/RAM.map_bb.hdb
Source/db/RAM.map_bb.logdb
Source/db/RAM.pre_map.cdb
Source/db/RAM.pre_map.hdb
Source/db/RAM.rtlv.hdb
Source/db/RAM.rtlv_sg.cdb
Source/db/RAM.rtlv_sg_swap.cdb
Source/db/RAM.sgdiff.cdb
Source/db/RAM.sgdiff.hdb
Source/db/RAM.sld_design_entry.sci
Source/db/RAM.sld_design_entry_dsc.sci
Source/db/RAM.smart_action.txt
Source/db/RAM.sta.qmsg
Source/db/RAM.sta.rdb
Source/db/RAM.sta_cmp.8_slow.tdb
Source/db/RAM.syn_hier_info
Source/db/RAM.tis_db_list.ddb
Source/db/RAM.tmw_info
Source/greybox_tmp/
Source/greybox_tmp/cbx_args.txt
Source/incremental_db/
Source/incremental_db/compiled_partitions/
Source/incremental_db/compiled_partitions/RAM.db_info
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.cbp
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.cdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.dfp
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.hdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.kpt
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.logdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.rcfdb
Source/incremental_db/compiled_partitions/RAM.root_partition.cmp.re.rcfdb
Source/incremental_db/compiled_partitions/RAM.root_partition.map.cbp
Source/incremental_db/compiled_partitions/RAM.root_partition.map.cdb
Source/incremental_db/compiled_partitions/RAM.root_partition.map.dpi
Source/incremental_db/compiled_partitions/RAM.root_partition.map.hdb
Source/incremental_db/compiled_partitions/RAM.root_partition.map.kpt
Source/incremental_db/README
Source/RAM.asm.rpt
Source/RAM.done
Source/RAM.eda.rpt
Source/RAM.fit.rpt
Source/RAM.fit.summary
Source/RAM.flow.rpt
Source/RAM.map.rpt
Source/RAM.map.summary
Source/RAM.pin
Source/RAM.pof
Source/RAM.qpf
Source/RAM.qsf
Source/RAM.sof
Source/RAM.sta.rpt
Source/RAM.sta.summary
Source/RAM.v
Source/RAM.v.bak
Source/ram4.bsf
Source/RAM4.cmp
Source/RAM4.inc
Source/RAM4.qip
Source/RAM4.v
Source/RAM4_bb.v
Source/RAM4_inst.v
Source/simulation/
Source/simulation/modelsim/
Source/simulation/modelsim/a_ram_tb.v
Source/simulation/modelsim/a_ram_tb.v.bak
Source/simulation/modelsim/cyclone_atoms.v
Source/simulation/modelsim/RAM.sft
Source/simulation/modelsim/RAM.vo
Source/simulation/modelsim/RAM_modelsim.xrf
Source/simulation/modelsim/RAM_v.sdo
Source/simulation/modelsim/RAM_v.sdo_typ.csd
Source/simulation/modelsim/tb.cr.mti
Source/simulation/modelsim/tb.mpf
Source/simulation/modelsim/vsim.wlf
Source/simulation/modelsim/work/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/verilog.prw
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/verilog.psm
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/_primary.dat
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/_primary.dbs
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s/_primary.vhd
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/verilog.prw
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/verilog.psm
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/_primary.dat
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/_primary.dbs
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e@a@s_@h@i@g@h/_primary.vhd
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.prw
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.psm
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
Source/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@
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