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文件名称:VGA_CTL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.41mb
  • 已下载：
    0次
  • 提 供 者：
    林***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

通过VGA显示一个汉字，用verilog编写，属于进阶实验-Through a VGA display Chinese characters, written with verilog, are advanced experimental
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VGA_CTL/Testbench/altera_mf.v
VGA_CTL/Testbench/VGA_tb.v
VGA_CTL/src/.VGA_CTL.v.swp
VGA_CTL/src/ROM.v
VGA_CTL/src/VGA_CHINESE_HONG.mif
VGA_CTL/src/VGA_CTL.v
VGA_CTL/Quartus/VGA_CTL.asm.rpt
VGA_CTL/Quartus/VGA_CTL.done
VGA_CTL/Quartus/VGA_CTL.dpf
VGA_CTL/Quartus/VGA_CTL.fit.rpt
VGA_CTL/Quartus/VGA_CTL.fit.smsg
VGA_CTL/Quartus/VGA_CTL.fit.summary
VGA_CTL/Quartus/VGA_CTL.flow.rpt
VGA_CTL/Quartus/VGA_CTL.map.rpt
VGA_CTL/Quartus/VGA_CTL.map.summary
VGA_CTL/Quartus/VGA_CTL.pin
VGA_CTL/Quartus/VGA_CTL.pof
VGA_CTL/Quartus/VGA_CTL.qpf
VGA_CTL/Quartus/VGA_CTL.qsf
VGA_CTL/Quartus/VGA_CTL.qws
VGA_CTL/Quartus/VGA_CTL.sof
VGA_CTL/Quartus/VGA_CTL.tan.rpt
VGA_CTL/Quartus/VGA_CTL.tan.summary
VGA_CTL/Quartus/incremental_db/README
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.atm
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.dfp
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.hdbx
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.kpt
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.logdb
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.cmp.rcf
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.atm
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.dpi
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.hdbx
VGA_CTL/Quartus/incremental_db/compiled_partitions/VGA_CTL.root_partition.map.kpt
VGA_CTL/Quartus/db/altsyncram_3881.tdf
VGA_CTL/Quartus/db/prev_cmp_VGA_CTL.asm.qmsg
VGA_CTL/Quartus/db/prev_cmp_VGA_CTL.fit.qmsg
VGA_CTL/Quartus/db/prev_cmp_VGA_CTL.map.qmsg
VGA_CTL/Quartus/db/prev_cmp_VGA_CTL.qmsg
VGA_CTL/Quartus/db/prev_cmp_VGA_CTL.tan.qmsg
VGA_CTL/Quartus/db/VGA.db_info
VGA_CTL/Quartus/db/VGA.eco.cdb
VGA_CTL/Quartus/db/VGA.sld_design_entry.sci
VGA_CTL/Quartus/db/VGA_CTL.db_info
VGA_CTL/Quartus/db/VGA_CTL.eco.cdb
VGA_CTL/Quartus/db/VGA_CTL.sld_design_entry.sci
VGA_CTL/Quartus/db/VGA_CTL_global_asgn_op.abo
VGA_CTL/modelsim/transcript
VGA_CTL/modelsim/VGA.cr.mti
VGA_CTL/modelsim/vga.do
VGA_CTL/modelsim/VGA.mpf
VGA_CTL/modelsim/vsim.wlf
VGA_CTL/modelsim/work/_info
VGA_CTL/modelsim/work/ttn_scale_cntr/_primary.dat
VGA_CTL/modelsim/work/ttn_scale_cntr/_primary.vhd
VGA_CTL/modelsim/work/ttn_n_cntr/_primary.dat
VGA_CTL/modelsim/work/ttn_n_cntr/_primary.vhd
VGA_CTL/modelsim/work/ttn_m_cntr/_primary.dat
VGA_CTL/modelsim/work/ttn_m_cntr/_primary.vhd
VGA_CTL/modelsim/work/stx_scale_cntr/_primary.dat
VGA_CTL/modelsim/work/stx_scale_cntr/_primary.vhd
VGA_CTL/modelsim/work/stx_n_cntr/_primary.dat
VGA_CTL/modelsim/work/stx_n_cntr/_primary.vhd
VGA_CTL/modelsim/work/stx_m_cntr/_primary.dat
VGA_CTL/modelsim/work/stx_m_cntr/_primary.vhd
VGA_CTL/modelsim/work/stratix_tx_outclk/_primary.dat
VGA_CTL/modelsim/work/stratix_tx_outclk/_primary.vhd
VGA_CTL/modelsim/work/stratix_lvds_rx/_primary.dat
VGA_CTL/modelsim/work/stratix_lvds_rx/_primary.vhd
VGA_CTL/modelsim/work/stratixii_tx_outclk/_primary.dat
VGA_CTL/modelsim/work/stratixii_tx_outclk/_primary.vhd
VGA_CTL/modelsim/work/stratixii_lvds_rx/_primary.dat
VGA_CTL/modelsim/work/stratixii_lvds_rx/_primary.vhd
VGA_CTL/modelsim/work/stratixiii_lvds_rx_dpa/_primary.dat
VGA_CTL/modelsim/work/stratixiii_lvds_rx_dpa/_primary.vhd
VGA_CTL/modelsim/work/stratixiii_lvds_rx_channel/_primary.dat
VGA_CTL/modelsim/work/stratixiii_lvds_rx_channel/_primary.vhd
VGA_CTL/modelsim/work/stratixiii_lvds_rx/_primary.dat
VGA_CTL/modelsim/work/stratixiii_lvds_rx/_primary.vhd
VGA_CTL/modelsim/work/stratixgx_dpa_lvds_rx/_primary.dat
VGA_CTL/modelsim/work/stratixgx_dpa_lvds_rx/_primary.vhd
VGA_CTL/modelsim/work/sld_virtual_jtag/_primary.dat
VGA_CTL/modelsim/work/sld_virtual_jtag/_primary.vhd
VGA_CTL/modelsim/work/sld_signaltap/_primary.dat
VGA_CTL/modelsim/work/sld_signaltap/_primary.vhd
VGA_CTL/modelsim/work/signal_gen/_primary.dat
VGA_CTL/modelsim/work/signal_gen/_primary.vhd
VGA_CTL/modelsim/work/scfifo/_primary.dat
VGA_CTL/modelsim/work/scfifo/_primary.vhd
VGA_CTL/modelsim/work/pll_iobuf/_primary.dat
VGA_CTL/modelsim/work/pll_iobuf/_primary.vhd
VGA_CTL/modelsim/work/parallel_add/_primary.dat
VGA_CTL/modelsim/work/parallel_add/_primary.vhd
VGA_CTL/modelsim/work/lcell/_primary.dat
VGA_CTL/modelsim/work/lcell/_primary.vhd
VGA_CTL/modelsim/work/jtag_tap_controller/_primary.dat
VGA_CTL/modelsim/work/jtag_tap_controller/_primary.vhd
VGA_CTL/modelsim/work/flexible_lvds_tx/_primary.dat
VGA_CTL/modelsim/work/flexible_lvds_tx/_primary.vhd
VGA_CTL/modelsim/work/flexible_lvds_rx/_primary.dat
VGA_CTL/modelsim/work/flexible_lvds_rx/_primary.vhd
VGA_CTL/modelsim/work/dummy_hub/_primary.dat
VGA_CTL/modelsim/work/dummy_hub/_primary.vhd
VGA_CTL/modelsim/work/dffp/_primary.dat
VGA_CTL/modelsim/work/dffp/_primary.vhd
VGA_CTL/modelsim/work/dcfifo_sync/_primary.dat
VGA_CTL/modelsim/work/dcfifo_sync/_primary.vhd
VGA_CTL/modelsim/work/dcfifo_mixed_widths/_primary.dat
VGA_CTL/modelsim/work/dcfifo_mixed_widths/_primary.vhd
VGA_CTL/modelsim/work/dcfifo_low_latency/_primary.dat
VGA_CTL/modelsim/work/dcfifo_low_latenc

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