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文件名称:Syn_FIFO

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.69mb
  • 已下载：
    0次
  • 提 供 者：
    d****
  • 相关连接：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

在libero环境下，FPGA如何使用ProASIC3/E的同步FIFO-In libero environment, FPGA using ProASIC3/E of the synchronous FIFO
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Syn_FIFO/SYN_FIFO/designer/impl1/designer.log
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top.adb
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top.dtf/verify.log
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top.ide_des
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top.pdb
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top.pdb.depends
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top.tcl
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top_fp/FIFO_top.log
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top_fp/FIFO_top.pro
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top_fp/projectData/FIFO_top.pdb
Syn_FIFO/SYN_FIFO/hdl/ctrl_FIFO.v
Syn_FIFO/SYN_FIFO/hdl/FIFO_top.v
Syn_FIFO/SYN_FIFO/hdl/rec.v
Syn_FIFO/SYN_FIFO/hdl/send.v
Syn_FIFO/SYN_FIFO/simulation/meminit.dat
Syn_FIFO/SYN_FIFO/simulation/modelsim.ini
Syn_FIFO/SYN_FIFO/simulation/modelsim.ini.sav
Syn_FIFO/SYN_FIFO/smartgen/smartgen.aws
Syn_FIFO/SYN_FIFO/smartgen/syn_fifo/syn_fifo.cxf
Syn_FIFO/SYN_FIFO/smartgen/syn_fifo/syn_fifo.gen
Syn_FIFO/SYN_FIFO/smartgen/syn_fifo/syn_fifo.log
Syn_FIFO/SYN_FIFO/smartgen/syn_fifo/syn_fifo.v
Syn_FIFO/SYN_FIFO/smartgen/syn_fifo_work.ixf
Syn_FIFO/SYN_FIFO/synthesis/.recordref
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.areasrr
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.edn
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.fse
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.htm
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.map
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.sap
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.sdf
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.srd
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.srm
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.srr
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.srs
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top.tlg
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top_sdc.sdc
Syn_FIFO/SYN_FIFO/synthesis/FIFO_top_syn.prj
Syn_FIFO/SYN_FIFO/synthesis/stdout.log
Syn_FIFO/SYN_FIFO/synthesis/syntmp/FIFO_top.msg
Syn_FIFO/SYN_FIFO/synthesis/syntmp/FIFO_top.plg
Syn_FIFO/SYN_FIFO/synthesis/syntmp/FIFO_top_flink.htm
Syn_FIFO/SYN_FIFO/synthesis/syntmp/FIFO_top_srr.htm
Syn_FIFO/SYN_FIFO/synthesis/syntmp/FIFO_top_toc.htm
Syn_FIFO/SYN_FIFO/synthesis/syntmp/sap.log
Syn_FIFO/SYN_FIFO/synthesis/traplog.tlg
Syn_FIFO/SYN_FIFO/SYN_FIFO.prj
Syn_FIFO/SYN_FIFO/viewdraw/vf/project.lst
Syn_FIFO/SYN_FIFO/viewdraw/viewdraw.ini
Syn_FIFO/Syn_FIFO_lab.rar
Syn_FIFO/同步FIFO实验例程.pdf
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top_fp/projectData
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top.dtf
Syn_FIFO/SYN_FIFO/designer/impl1/FIFO_top_fp
Syn_FIFO/SYN_FIFO/designer/impl1/simulation
Syn_FIFO/SYN_FIFO/designer/impl1
Syn_FIFO/SYN_FIFO/smartgen/syn_fifo
Syn_FIFO/SYN_FIFO/synthesis/syntmp
Syn_FIFO/SYN_FIFO/viewdraw/vf
Syn_FIFO/SYN_FIFO/designer
Syn_FIFO/SYN_FIFO/hdl
Syn_FIFO/SYN_FIFO/simulation
Syn_FIFO/SYN_FIFO/smartgen
Syn_FIFO/SYN_FIFO/synthesis
Syn_FIFO/SYN_FIFO/viewdraw
Syn_FIFO/SYN_FIFO
Syn_FIFO

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