文件名称:No.4
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- 上传时间:2012-11-16
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文件大小:334.45kb
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已下载:0次
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使用C8051F005开发板,控制FPGA和高速DA来DDS,两路DDS输出,90或180或0相差-Using the C8051F005 development board, the control FPGA and high-speed DA to DDS, two DDS output, a difference of 90 or 180 or 0
(系统自动生成,下载前可以参看下载内容)
下载文件列表
No.4/
No.4/Desktop.ini
No.4/FPGA_DDS000/
No.4/FPGA_DDS000/1.wsp
No.4/FPGA_DDS000/c8051F000.h
No.4/FPGA_DDS000/constant.#1
No.4/FPGA_DDS000/constant.#2
No.4/FPGA_DDS000/constant.#3
No.4/FPGA_DDS000/constant.h
No.4/FPGA_DDS000/cyglink.txt
No.4/FPGA_DDS000/Desktop.ini
No.4/FPGA_DDS000/f_define.#1
No.4/FPGA_DDS000/f_define.#2
No.4/FPGA_DDS000/f_define.#3
No.4/FPGA_DDS000/f_define.h
No.4/FPGA_DDS000/MAIN
No.4/FPGA_DDS000/main.#1
No.4/FPGA_DDS000/main.#2
No.4/FPGA_DDS000/main.#3
No.4/FPGA_DDS000/main.c
No.4/FPGA_DDS000/main.LST
No.4/FPGA_DDS000/MAIN.M51
No.4/FPGA_DDS000/main.OBJ
No.4/FPGA_DDS000/tmp.out
No.4/FPGA_DDS000/ziku.h
No.4/FPGA_DDS001/
No.4/FPGA_DDS001/1.wsp
No.4/FPGA_DDS001/c8051F000.h
No.4/FPGA_DDS001/constant.#1
No.4/FPGA_DDS001/constant.#2
No.4/FPGA_DDS001/constant.#3
No.4/FPGA_DDS001/constant.h
No.4/FPGA_DDS001/cyglink.txt
No.4/FPGA_DDS001/Desktop.ini
No.4/FPGA_DDS001/f_define.#1
No.4/FPGA_DDS001/f_define.#2
No.4/FPGA_DDS001/f_define.#3
No.4/FPGA_DDS001/f_define.h
No.4/FPGA_DDS001/MAIN
No.4/FPGA_DDS001/main.#1
No.4/FPGA_DDS001/main.#2
No.4/FPGA_DDS001/main.#3
No.4/FPGA_DDS001/main.c
No.4/FPGA_DDS001/main.LST
No.4/FPGA_DDS001/MAIN.M51
No.4/FPGA_DDS001/main.OBJ
No.4/FPGA_DDS001/tmp.out
No.4/FPGA_DDS001/ziku.#1
No.4/FPGA_DDS001/ziku.#2
No.4/FPGA_DDS001/ziku.#3
No.4/FPGA_DDS001/ziku.h
No.4/FPGA_DDS066_1/
No.4/FPGA_DDS066_1/1.wsp
No.4/FPGA_DDS066_1/c8051F000.h
No.4/FPGA_DDS066_1/constant.#1
No.4/FPGA_DDS066_1/constant.#2
No.4/FPGA_DDS066_1/constant.#3
No.4/FPGA_DDS066_1/constant.h
No.4/FPGA_DDS066_1/cyglink.txt
No.4/FPGA_DDS066_1/Desktop.ini
No.4/FPGA_DDS066_1/f_define.#1
No.4/FPGA_DDS066_1/f_define.#2
No.4/FPGA_DDS066_1/f_define.#3
No.4/FPGA_DDS066_1/f_define.h
No.4/FPGA_DDS066_1/MAIN
No.4/FPGA_DDS066_1/main.#1
No.4/FPGA_DDS066_1/main.#2
No.4/FPGA_DDS066_1/main.#3
No.4/FPGA_DDS066_1/main.c
No.4/FPGA_DDS066_1/main.LST
No.4/FPGA_DDS066_1/MAIN.M51
No.4/FPGA_DDS066_1/main.OBJ
No.4/FPGA_DDS066_1/tmp.out
No.4/FPGA_DDS066_1/ziku.#1
No.4/FPGA_DDS066_1/ziku.#2
No.4/FPGA_DDS066_1/ziku.#3
No.4/FPGA_DDS066_1/ziku.h
No.4/FPGA_DDS066_2/
No.4/FPGA_DDS066_2/1.wsp
No.4/FPGA_DDS066_2/c8051F000.h
No.4/FPGA_DDS066_2/constant.#1
No.4/FPGA_DDS066_2/constant.#2
No.4/FPGA_DDS066_2/constant.#3
No.4/FPGA_DDS066_2/constant.h
No.4/FPGA_DDS066_2/cyglink.txt
No.4/FPGA_DDS066_2/Desktop.ini
No.4/FPGA_DDS066_2/f_define.#1
No.4/FPGA_DDS066_2/f_define.#2
No.4/FPGA_DDS066_2/f_define.#3
No.4/FPGA_DDS066_2/f_define.h
No.4/FPGA_DDS066_2/MAIN
No.4/FPGA_DDS066_2/main.#1
No.4/FPGA_DDS066_2/main.#2
No.4/FPGA_DDS066_2/main.#3
No.4/FPGA_DDS066_2/main.c
No.4/FPGA_DDS066_2/main.LST
No.4/FPGA_DDS066_2/MAIN.M51
No.4/FPGA_DDS066_2/main.OBJ
No.4/FPGA_DDS066_2/tmp.out
No.4/FPGA_DDS066_2/ziku.#1
No.4/FPGA_DDS066_2/ziku.#2
No.4/FPGA_DDS066_2/ziku.#3
No.4/FPGA_DDS066_2/ziku.h
No.4/readme.txt
No.4/Desktop.ini
No.4/FPGA_DDS000/
No.4/FPGA_DDS000/1.wsp
No.4/FPGA_DDS000/c8051F000.h
No.4/FPGA_DDS000/constant.#1
No.4/FPGA_DDS000/constant.#2
No.4/FPGA_DDS000/constant.#3
No.4/FPGA_DDS000/constant.h
No.4/FPGA_DDS000/cyglink.txt
No.4/FPGA_DDS000/Desktop.ini
No.4/FPGA_DDS000/f_define.#1
No.4/FPGA_DDS000/f_define.#2
No.4/FPGA_DDS000/f_define.#3
No.4/FPGA_DDS000/f_define.h
No.4/FPGA_DDS000/MAIN
No.4/FPGA_DDS000/main.#1
No.4/FPGA_DDS000/main.#2
No.4/FPGA_DDS000/main.#3
No.4/FPGA_DDS000/main.c
No.4/FPGA_DDS000/main.LST
No.4/FPGA_DDS000/MAIN.M51
No.4/FPGA_DDS000/main.OBJ
No.4/FPGA_DDS000/tmp.out
No.4/FPGA_DDS000/ziku.h
No.4/FPGA_DDS001/
No.4/FPGA_DDS001/1.wsp
No.4/FPGA_DDS001/c8051F000.h
No.4/FPGA_DDS001/constant.#1
No.4/FPGA_DDS001/constant.#2
No.4/FPGA_DDS001/constant.#3
No.4/FPGA_DDS001/constant.h
No.4/FPGA_DDS001/cyglink.txt
No.4/FPGA_DDS001/Desktop.ini
No.4/FPGA_DDS001/f_define.#1
No.4/FPGA_DDS001/f_define.#2
No.4/FPGA_DDS001/f_define.#3
No.4/FPGA_DDS001/f_define.h
No.4/FPGA_DDS001/MAIN
No.4/FPGA_DDS001/main.#1
No.4/FPGA_DDS001/main.#2
No.4/FPGA_DDS001/main.#3
No.4/FPGA_DDS001/main.c
No.4/FPGA_DDS001/main.LST
No.4/FPGA_DDS001/MAIN.M51
No.4/FPGA_DDS001/main.OBJ
No.4/FPGA_DDS001/tmp.out
No.4/FPGA_DDS001/ziku.#1
No.4/FPGA_DDS001/ziku.#2
No.4/FPGA_DDS001/ziku.#3
No.4/FPGA_DDS001/ziku.h
No.4/FPGA_DDS066_1/
No.4/FPGA_DDS066_1/1.wsp
No.4/FPGA_DDS066_1/c8051F000.h
No.4/FPGA_DDS066_1/constant.#1
No.4/FPGA_DDS066_1/constant.#2
No.4/FPGA_DDS066_1/constant.#3
No.4/FPGA_DDS066_1/constant.h
No.4/FPGA_DDS066_1/cyglink.txt
No.4/FPGA_DDS066_1/Desktop.ini
No.4/FPGA_DDS066_1/f_define.#1
No.4/FPGA_DDS066_1/f_define.#2
No.4/FPGA_DDS066_1/f_define.#3
No.4/FPGA_DDS066_1/f_define.h
No.4/FPGA_DDS066_1/MAIN
No.4/FPGA_DDS066_1/main.#1
No.4/FPGA_DDS066_1/main.#2
No.4/FPGA_DDS066_1/main.#3
No.4/FPGA_DDS066_1/main.c
No.4/FPGA_DDS066_1/main.LST
No.4/FPGA_DDS066_1/MAIN.M51
No.4/FPGA_DDS066_1/main.OBJ
No.4/FPGA_DDS066_1/tmp.out
No.4/FPGA_DDS066_1/ziku.#1
No.4/FPGA_DDS066_1/ziku.#2
No.4/FPGA_DDS066_1/ziku.#3
No.4/FPGA_DDS066_1/ziku.h
No.4/FPGA_DDS066_2/
No.4/FPGA_DDS066_2/1.wsp
No.4/FPGA_DDS066_2/c8051F000.h
No.4/FPGA_DDS066_2/constant.#1
No.4/FPGA_DDS066_2/constant.#2
No.4/FPGA_DDS066_2/constant.#3
No.4/FPGA_DDS066_2/constant.h
No.4/FPGA_DDS066_2/cyglink.txt
No.4/FPGA_DDS066_2/Desktop.ini
No.4/FPGA_DDS066_2/f_define.#1
No.4/FPGA_DDS066_2/f_define.#2
No.4/FPGA_DDS066_2/f_define.#3
No.4/FPGA_DDS066_2/f_define.h
No.4/FPGA_DDS066_2/MAIN
No.4/FPGA_DDS066_2/main.#1
No.4/FPGA_DDS066_2/main.#2
No.4/FPGA_DDS066_2/main.#3
No.4/FPGA_DDS066_2/main.c
No.4/FPGA_DDS066_2/main.LST
No.4/FPGA_DDS066_2/MAIN.M51
No.4/FPGA_DDS066_2/main.OBJ
No.4/FPGA_DDS066_2/tmp.out
No.4/FPGA_DDS066_2/ziku.#1
No.4/FPGA_DDS066_2/ziku.#2
No.4/FPGA_DDS066_2/ziku.#3
No.4/FPGA_DDS066_2/ziku.h
No.4/readme.txt
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