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文件名称:GateDriver

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    5.43mb
  • 已下载：
    0次
  • 提 供 者：
    zho***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

actel fpga fusion kit 操作端口-actel fpga fusion kit operating port
相关搜索： actel

(系统自动生成,下载前可以参看下载内容)

下载文件列表

门驱动实验/Source/GateDrive_lab/GateDrive_top.v
门驱动实验/Project/GateDrive_lab/GateDrive_lab.prj
门驱动实验/Project/GateDrive_lab/viewdraw/vf/project.lst
门驱动实验/Project/GateDrive_lab/viewdraw/viewdraw.ini
门驱动实验/Project/GateDrive_lab/synthesis/.recordref
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.areasrr
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.edn
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.fse
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.htm
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.map
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.sap
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.sdf
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.srd
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.srm
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.srr
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.srs
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top.tlg
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top_drc.rpt
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top_sdc.sdc
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top_syn.prd
门驱动实验/Project/GateDrive_lab/synthesis/stdout.log
门驱动实验/Project/GateDrive_lab/synthesis/traplog.tlg
门驱动实验/Project/GateDrive_lab/synthesis/syntmp/GateDrive_top.msg
门驱动实验/Project/GateDrive_lab/synthesis/syntmp/GateDrive_top.plg
门驱动实验/Project/GateDrive_lab/synthesis/syntmp/GateDrive_top_flink.htm
门驱动实验/Project/GateDrive_lab/synthesis/syntmp/GateDrive_top_srr.htm
门驱动实验/Project/GateDrive_lab/synthesis/syntmp/GateDrive_top_toc.htm
门驱动实验/Project/GateDrive_lab/synthesis/syntmp/sap.log
门驱动实验/Project/GateDrive_lab/synthesis/GateDrive_top_syn.prj
门驱动实验/Project/GateDrive_lab/stimulus/BtimErrors.log
门驱动实验/Project/GateDrive_lab/stimulus/GateDrive_top.dsk
门驱动实验/Project/GateDrive_lab/stimulus/GateDrive_top.hpj
门驱动实验/Project/GateDrive_lab/stimulus/GateDrive_top_tbench.btim
门驱动实验/Project/GateDrive_lab/stimulus/GateDrive_top_tbench.v
门驱动实验/Project/GateDrive_lab/stimulus/files_to_build.txt
门驱动实验/Project/GateDrive_lab/stimulus/waveperl.log
门驱动实验/Project/GateDrive_lab/smartgen/PLL1_work.ixf
门驱动实验/Project/GateDrive_lab/smartgen/analog_work.ixf
门驱动实验/Project/GateDrive_lab/smartgen/flashmem_work.ixf
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem.cfg
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem.cxf
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem.efc
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem.gen
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem.log
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem.mem
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem.v
门驱动实验/Project/GateDrive_lab/smartgen/flashmem/flashmem_init_wrapper.v
门驱动实验/Project/GateDrive_lab/smartgen/common/commonFileInventory.xml
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/assc.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/initcfg.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/initcfg_xa.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/initcfg_xb.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/initcfg_xc.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/initcfg_xd.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/initcfg_xe.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/initcfg_xf.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/smev.v
门驱动实验/Project/GateDrive_lab/smartgen/common/verilog/smtr.v
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog.cfg
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog.cxf
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog.gen
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog.log
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog.ncf
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog.v
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_acm.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_acm_ram.hex
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_acm_ram_R0C0.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_assc.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_assc_ram.hex
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_assc_ram.v
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_assc_ram_R0C0.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_assc_wrapper.v
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smev.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smev_ram.hex
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smev_ram.v
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smev_ram_R0C0.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smev_wrapper.v
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smtr.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smtr_ram.hex
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smtr_ram.v
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smtr_ram_R0C0.mem
门驱动实验/Project/GateDrive_lab/smartgen/analog/analog_smtr_wrapper.v
门驱动实验/Project/GateDrive_lab/smartgen/PLL1/PLL1.cxf
门驱动实验/Project/GateDrive_lab/smartgen/PLL1/PLL1.gen
门驱动实验/Project/GateDrive_lab/smartgen/PLL1/PLL1.log
门驱动实验/Project/GateDrive_lab/smartgen/PLL1/PLL1.v
门驱动实验/Project/GateDrive_lab/smartgen/PLL1/assert.log
门驱动实验/Project/GateD

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