uart/smartgen/smartgen.aws
uart/hdl/speed_select.v
uart/hdl/my_uart_tx.v
uart/hdl/my_uart_top.v
uart/hdl/my_uart_rx.v
uart/viewdraw/vf/project.lst
uart/viewdraw/viewdraw.ini
uart/simulation/modelsim.ini.sav
uart/simulation/modelsim.ini
uart/synthesis/stdout.log
uart/synthesis/syntmp/sap.log
uart/synthesis/syntmp/my_uart_top.plg
uart/synthesis/backup/my_uart_top.srr
uart/synthesis/run_options.txt
uart/synthesis/my_uart_top.tlg
uart/synthesis/my_uart_top.sap
uart/synthesis/my_uart_top.fse
uart/synthesis/my_uart_top.szr
uart/synthesis/traplog.tlg
uart/synthesis/.recordref
uart/synthesis/my_uart_top.srd
uart/synthesis/my_uart_top.srm
uart/synthesis/my_uart_top.map
uart/synthesis/my_uart_top.edn
uart/synthesis/my_uart_top.sdf
uart/synthesis/my_uart_top.pdc
uart/synthesis/my_uart_top_sdc.sdc
uart/synthesis/my_uart_top.so
uart/synthesis/my_uart_top.areasrr
uart/synthesis/my_uart_top_syn.prj
uart/synthesis/my_uart_top.srr
uart/synthesis/my_uart_top.srs
uart/designer/impl1/my_uart_top.ide_des
uart/designer/impl1/my_uart_rx.ide_des
uart/designer/impl1/speed_select.ide_des
uart/designer/impl1/my_uart_top.tcl
uart/designer/impl1/my_uart_top.dtf/verify.log
uart/designer/impl1/my_uart_top.pdb
uart/designer/impl1/my_uart_top.pdb.depends
uart/designer/impl1/designer.log
uart/designer/impl1/my_uart_top_fp/my_uart_top.pro
uart/designer/impl1/my_uart_top_fp/$$FlashPro_FPBBALTLPT1.L$$
uart/designer/impl1/my_uart_top_fp/projectData/my_uart_top.pdb
uart/designer/impl1/my_uart_top_fp/my_uart_top.log
uart/designer/impl1/my_uart_tx.ide_des
uart/designer/impl1/my_uart_top.adb
uart/uart.prj
uart/designer/impl1/my_uart_top_fp/projectData
uart/designer/impl1/simulation
uart/designer/impl1/my_uart_top.dtf
uart/designer/impl1/my_uart_top_fp
uart/viewdraw/vf
uart/viewdraw/sch
uart/viewdraw/sym
uart/viewdraw/wir
uart/synthesis/syntmp
uart/synthesis/coreip
uart/synthesis/backup
uart/designer/impl1
uart/smartgen
uart/hdl
uart/constraint
uart/viewdraw
uart/component
uart/coreconsole
uart/simulation
uart/synthesis
uart/phy_synthesis
uart/stimulus
uart/designer
uart