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文件名称:2259647AlteraSDR-SDRAM

  • 所属分类：
    MiddleWare
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    760.15kb
  • 已下载：
    0次
  • 提 供 者：
    w***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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介绍说明－－下载内容来自于网络，使用问题请自行百度

Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our method for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences, we first search for homologues in a database of interacting domains (DBID) of known three-dimensional complex structures. Pairs of sequences homologous to a known interacting
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下载文件列表

2259647Al''teraSDR-SDRAM/doc/readme.txt
2259647Al''teraSDR-SDRAM/doc/sdr_sdram.pdf
2259647Al''teraSDR-SDRAM/model/mt48lc8m16a2.v
2259647Al''teraSDR-SDRAM/route/PLL1.v
2259647Al''teraSDR-SDRAM/route/sdr_sdram.csf
2259647Al''teraSDR-SDRAM/route/sdr_sdram.esf
2259647Al''teraSDR-SDRAM/route/sdr_sdram.vqm
2259647Al''teraSDR-SDRAM/simulation/modelsim.ini
2259647Al''teraSDR-SDRAM/simulation/readme.txt
2259647Al''teraSDR-SDRAM/simulation/sdr_sdram_tb.v
2259647Al''teraSDR-SDRAM/simulation/work/altclklock/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/altclklock/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/altclklock/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/command/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/command/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/command/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/control_interface/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/control_interface/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/control_interface/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/mt48lc8m16a2/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/mt48lc8m16a2/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/mt48lc8m16a2/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/pll1/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/pll1/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/pll1/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/sdr_data_path/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/sdr_data_path/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/sdr_data_path/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram_tb/verilog.psm
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram_tb/_primary.dat
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram_tb/_primary.vhd
2259647Al''teraSDR-SDRAM/simulation/work/_info
2259647Al''teraSDR-SDRAM/source/altclklock.v
2259647Al''teraSDR-SDRAM/source/Command.v
2259647Al''teraSDR-SDRAM/source/compile_all.v
2259647Al''teraSDR-SDRAM/source/control_interface.v
2259647Al''teraSDR-SDRAM/source/Params.v
2259647Al''teraSDR-SDRAM/source/PLL1.v
2259647Al''teraSDR-SDRAM/source/sdr_data_path.v
2259647Al''teraSDR-SDRAM/source/sdr_sdram.v
2259647Al''teraSDR-SDRAM/synthesis/synplicity/sdr_sdram.prj
2259647Al''teraSDR-SDRAM/2259647Al''teraSDR-SDRAM/simulation/work/altclklock
2259647Al''teraSDR-SDRAM/simulation/work/command
2259647Al''teraSDR-SDRAM/simulation/work/control_interface
2259647Al''teraSDR-SDRAM/simulation/work/mt48lc8m16a2
2259647Al''teraSDR-SDRAM/simulation/work/pll1
2259647Al''teraSDR-SDRAM/simulation/work/sdr_data_path
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram
2259647Al''teraSDR-SDRAM/simulation/work/sdr_sdram_tb
2259647Al''teraSDR-SDRAM/simulation/work
2259647Al''teraSDR-SDRAM/synthesis/synplicity
2259647Al''teraSDR-SDRAM/doc
2259647Al''teraSDR-SDRAM/model
2259647Al''teraSDR-SDRAM/route
2259647Al''teraSDR-SDRAM/simulation
2259647Al''teraSDR-SDRAM/source
2259647Al''teraSDR-SDRAM/synthesis
2259647Al''teraSDR-SDRAM

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