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文件名称:usb2.0_funct_ip

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    192.6kb
  • 已下载：
    0次
  • 提 供 者：
    苏****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

一个USB2.0的IP核（详细verilog源码和文档），很不错的参考设计-A USB2.0 IP core (for details verilog source code and documentation), it is a good reference design
(系统自动生成,下载前可以参看下载内容)

下载文件列表

usb2.0_funct_ip/bench/CVS/Entries
usb2.0_funct_ip/bench/CVS/Repository
usb2.0_funct_ip/bench/CVS/Root
usb2.0_funct_ip/bench/verilog/CVS/Entries
usb2.0_funct_ip/bench/verilog/CVS/Repository
usb2.0_funct_ip/bench/verilog/CVS/Root
usb2.0_funct_ip/doc/CVS/Entries
usb2.0_funct_ip/doc/CVS/Repository
usb2.0_funct_ip/doc/CVS/Root
usb2.0_funct_ip/doc/README.txt
usb2.0_funct_ip/doc/STATUS.txt
usb2.0_funct_ip/doc/usb_doc.pdf
usb2.0_funct_ip/rtl/CVS/Entries
usb2.0_funct_ip/rtl/CVS/Repository
usb2.0_funct_ip/rtl/CVS/Root
usb2.0_funct_ip/rtl/verilog/CVS/Entries
usb2.0_funct_ip/rtl/verilog/CVS/Repository
usb2.0_funct_ip/rtl/verilog/CVS/Root
usb2.0_funct_ip/rtl/verilog/usbf_crc16.v
usb2.0_funct_ip/rtl/verilog/usbf_crc5.v
usb2.0_funct_ip/rtl/verilog/usbf_defines.v
usb2.0_funct_ip/rtl/verilog/usbf_ep_rf.v
usb2.0_funct_ip/rtl/verilog/usbf_ep_rf_dummy.v
usb2.0_funct_ip/rtl/verilog/usbf_idma.v
usb2.0_funct_ip/rtl/verilog/usbf_mem_arb.v
usb2.0_funct_ip/rtl/verilog/usbf_pa.v
usb2.0_funct_ip/rtl/verilog/usbf_pd.v
usb2.0_funct_ip/rtl/verilog/usbf_pe.v
usb2.0_funct_ip/rtl/verilog/usbf_pl.v
usb2.0_funct_ip/rtl/verilog/usbf_rf.v
usb2.0_funct_ip/rtl/verilog/usbf_top.v
usb2.0_funct_ip/rtl/verilog/usbf_utmi_if.v
usb2.0_funct_ip/rtl/verilog/usbf_utmi_ls.v
usb2.0_funct_ip/rtl/verilog/usbf_wb.v
usb2.0_funct_ip/sim/CVS/Entries
usb2.0_funct_ip/sim/CVS/Repository
usb2.0_funct_ip/sim/CVS/Root
usb2.0_funct_ip/sim/rtl_sim/bin/CVS/Entries
usb2.0_funct_ip/sim/rtl_sim/bin/CVS/Repository
usb2.0_funct_ip/sim/rtl_sim/bin/CVS/Root
usb2.0_funct_ip/sim/rtl_sim/CVS/Entries
usb2.0_funct_ip/sim/rtl_sim/CVS/Repository
usb2.0_funct_ip/sim/rtl_sim/CVS/Root
usb2.0_funct_ip/sim/rtl_sim/run/CVS/Entries
usb2.0_funct_ip/sim/rtl_sim/run/CVS/Repository
usb2.0_funct_ip/sim/rtl_sim/run/CVS/Root
usb2.0_funct_ip/syn/bin/comp.dc
usb2.0_funct_ip/syn/bin/CVS/Entries
usb2.0_funct_ip/syn/bin/CVS/Repository
usb2.0_funct_ip/syn/bin/CVS/Root
usb2.0_funct_ip/syn/bin/design_spec.dc
usb2.0_funct_ip/syn/bin/lib_spec.dc
usb2.0_funct_ip/syn/bin/read.dc
usb2.0_funct_ip/syn/CVS/Entries
usb2.0_funct_ip/syn/CVS/Repository
usb2.0_funct_ip/syn/CVS/Root
usb2.0_funct_ip/syn/log/CVS/Entries
usb2.0_funct_ip/syn/log/CVS/Repository
usb2.0_funct_ip/syn/log/CVS/Root
usb2.0_funct_ip/syn/out/CVS/Entries
usb2.0_funct_ip/syn/out/CVS/Repository
usb2.0_funct_ip/syn/out/CVS/Root
usb2.0_funct_ip/syn/run/CVS/Entries
usb2.0_funct_ip/syn/run/CVS/Repository
usb2.0_funct_ip/syn/run/CVS/Root
usb2.0_funct_ip/sim/rtl_sim/bin/CVS
usb2.0_funct_ip/sim/rtl_sim/run/CVS
usb2.0_funct_ip/bench/verilog/CVS
usb2.0_funct_ip/rtl/verilog/CVS
usb2.0_funct_ip/sim/rtl_sim/bin
usb2.0_funct_ip/sim/rtl_sim/CVS
usb2.0_funct_ip/sim/rtl_sim/run
usb2.0_funct_ip/syn/bin/CVS
usb2.0_funct_ip/syn/log/CVS
usb2.0_funct_ip/syn/out/CVS
usb2.0_funct_ip/syn/run/CVS
usb2.0_funct_ip/bench/CVS
usb2.0_funct_ip/bench/verilog
usb2.0_funct_ip/doc/CVS
usb2.0_funct_ip/rtl/CVS
usb2.0_funct_ip/rtl/verilog
usb2.0_funct_ip/sim/CVS
usb2.0_funct_ip/sim/rtl_sim
usb2.0_funct_ip/syn/bin
usb2.0_funct_ip/syn/CVS
usb2.0_funct_ip/syn/log
usb2.0_funct_ip/syn/out
usb2.0_funct_ip/syn/run
usb2.0_funct_ip/bench
usb2.0_funct_ip/doc
usb2.0_funct_ip/rtl
usb2.0_funct_ip/sim
usb2.0_funct_ip/syn
usb2.0_funct_ip

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