对一种改进的不恢复余数的开方算法(non - restoring square - root algorithm)进行了讨论 ,并将其应用于基于

IEEE 754 标准的32 位浮点格式的开方运算中 ,以一款 FPGA 为载体 ,实现了进行运算的基本电路。对目前存在的几种开方

算法进行了评述 ,分析了他们的优缺点 ,提出了改进的不恢复余数开方算法模块化的设计思路与关键电路 ,并分析了仿真和

逻辑综合的结果 ,证明了该算法运算速度较快且占用资源极少的特点。-An improved non-recovery of the remainder of the square root algorithm (non- restoring square- root algorithm) are discussed and applied based on the IEEE 754 standard 32-bit floating point format in the square root to a FPGA as the carrier, to achieve the basic circuit operation. Evolution of several existing algorithms have been reviewed, analyzed their advantages and disadvantages of the proposed improvements do not restore the remainder of the modular square root algorithm and key circuit design ideas, and analyzed the results of simulation and logic synthesis, that the arithmetic operations faster and take up very little resources characteristics.