CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:LVDS-application-Verilog-HDL-code

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    411.88kb
  • 已下载：
    0次
  • 提 供 者：
    v*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

LVDS的应用的Verilog HDL例子程序-LVDS example of the application procedures for the Verilog HDL
相关搜索： LVDS Verilog lvds

(系统自动生成,下载前可以参看下载内容)

下载文件列表

sim/comp_altera_lib.do
sim/comp_gate.do
sim/diff_io_top.vo
sim/diff_io_top_v.sdo
sim/gate_sim.do
sim/stratix/@p@r@i@m_@d@f@f@e/verilog.asm
sim/stratix/@p@r@i@m_@d@f@f@e/_primary.dat
sim/stratix/@p@r@i@m_@d@f@f@e/_primary.vhd
sim/stratix/and1/verilog.asm
sim/stratix/and1/_primary.dat
sim/stratix/and1/_primary.vhd
sim/stratix/and16/verilog.asm
sim/stratix/and16/_primary.dat
sim/stratix/and16/_primary.vhd
sim/stratix/b17mux21/verilog.asm
sim/stratix/b17mux21/_primary.dat
sim/stratix/b17mux21/_primary.vhd
sim/stratix/b5mux21/verilog.asm
sim/stratix/b5mux21/_primary.dat
sim/stratix/b5mux21/_primary.vhd
sim/stratix/bmux21/verilog.asm
sim/stratix/bmux21/_primary.dat
sim/stratix/bmux21/_primary.vhd
sim/stratix/dffe/verilog.asm
sim/stratix/dffe/_primary.dat
sim/stratix/dffe/_primary.vhd
sim/stratix/latch/verilog.asm
sim/stratix/latch/_primary.dat
sim/stratix/latch/_primary.vhd
sim/stratix/mux21/verilog.asm
sim/stratix/mux21/_primary.dat
sim/stratix/mux21/_primary.vhd
sim/stratix/m_cntr/verilog.asm
sim/stratix/m_cntr/_primary.dat
sim/stratix/m_cntr/_primary.vhd
sim/stratix/nmux21/verilog.asm
sim/stratix/nmux21/_primary.dat
sim/stratix/nmux21/_primary.vhd
sim/stratix/n_cntr/verilog.asm
sim/stratix/n_cntr/_primary.dat
sim/stratix/n_cntr/_primary.vhd
sim/stratix/scale_cntr/verilog.asm
sim/stratix/scale_cntr/_primary.dat
sim/stratix/scale_cntr/_primary.vhd
sim/stratix/stratix_asynch_io/verilog.asm
sim/stratix/stratix_asynch_io/_primary.dat
sim/stratix/stratix_asynch_io/_primary.vhd
sim/stratix/stratix_asynch_lcell/verilog.asm
sim/stratix/stratix_asynch_lcell/_primary.dat
sim/stratix/stratix_asynch_lcell/_primary.vhd
sim/stratix/stratix_crcblock/verilog.asm
sim/stratix/stratix_crcblock/_primary.dat
sim/stratix/stratix_crcblock/_primary.vhd
sim/stratix/stratix_io/verilog.asm
sim/stratix/stratix_io/_primary.dat
sim/stratix/stratix_io/_primary.vhd
sim/stratix/stratix_io_register/verilog.asm
sim/stratix/stratix_io_register/_primary.dat
sim/stratix/stratix_io_register/_primary.vhd
sim/stratix/stratix_jtag/verilog.asm
sim/stratix/stratix_jtag/_primary.dat
sim/stratix/stratix_jtag/_primary.vhd
sim/stratix/stratix_lcell/verilog.asm
sim/stratix/stratix_lcell/_primary.dat
sim/stratix/stratix_lcell/_primary.vhd
sim/stratix/stratix_lcell_register/verilog.asm
sim/stratix/stratix_lcell_register/_primary.dat
sim/stratix/stratix_lcell_register/_primary.vhd
sim/stratix/stratix_lvds_receiver/verilog.asm
sim/stratix/stratix_lvds_receiver/_primary.dat
sim/stratix/stratix_lvds_receiver/_primary.vhd
sim/stratix/stratix_lvds_rx_parallel_register/verilog.asm
sim/stratix/stratix_lvds_rx_parallel_register/_primary.dat
sim/stratix/stratix_lvds_rx_parallel_register/_primary.vhd
sim/stratix/stratix_lvds_transmitter/verilog.asm
sim/stratix/stratix_lvds_transmitter/_primary.dat
sim/stratix/stratix_lvds_transmitter/_primary.vhd
sim/stratix/stratix_lvds_tx_out_block/verilog.asm
sim/stratix/stratix_lvds_tx_out_block/_primary.dat
sim/stratix/stratix_lvds_tx_out_block/_primary.vhd
sim/stratix/stratix_lvds_tx_parallel_register/verilog.asm
sim/stratix/stratix_lvds_tx_parallel_register/_primary.dat
sim/stratix/stratix_lvds_tx_parallel_register/_primary.vhd
sim/stratix/stratix_mac_mult/verilog.asm
sim/stratix/stratix_mac_mult/_primary.dat
sim/stratix/stratix_mac_mult/_primary.vhd
sim/stratix/stratix_mac_mult_internal/verilog.asm
sim/stratix/stratix_mac_mult_internal/_primary.dat
sim/stratix/stratix_mac_mult_internal/_primary.vhd
sim/stratix/stratix_mac_out/verilog.asm
sim/stratix/stratix_mac_out/_primary.dat
sim/stratix/stratix_mac_out/_primary.vhd
sim/stratix/stratix_mac_out_internal/verilog.asm
sim/stratix/stratix_mac_out_internal/_primary.dat
sim/stratix/stratix_mac_out_internal/_primary.vhd
sim/stratix/stratix_mac_register/verilog.asm
sim/stratix/stratix_mac_register/_primary.dat
sim/stratix/stratix_mac_register/_primary.vhd
sim/stratix/stratix_pll/verilog.asm
sim/stratix/stratix_pll/_primary.dat
sim/stratix/stratix_pll/_primary.vhd
sim/stratix/stratix_ram_block/verilog.asm
sim/stratix/stratix_ram_block/_primary.dat
sim/stratix/stratix_ram_block/_primary.vhd
sim/stratix/stratix_ram_internal/verilog.asm
sim/stratix/stratix_ram_internal/_primary.dat
sim/stratix/stratix_ram_internal/_primary.vhd
sim/stratix/stratix_ram_register/verilog.asm
sim/stratix/stratix_ram_register/_primary.dat
sim/stratix/stratix_ram_register/_primary.vhd
sim/stratix/stratix_rublock/verilog.asm
sim/stratix/stratix_rublock/_primary.dat
sim/stratix/stratix_rublock/_primary.vhd
sim/stratix/_info
sim/testbench.v
src/Diff_io_top.v
src/lvds_rx.v
src/lvds_tx.v
src/mult.v
src/transcript
sim/stratix/@p@r@i@m_@d@f@f@e
sim/stratix/and1
sim/stratix/and16
sim/stratix/b17mux21
sim/stratix/b5mux21
sim/stratix/bmux21
sim/stratix/dffe
sim/stratix/latch
sim/stratix/mux21
sim/stratix/m_cntr
sim/stratix/nmux21
sim/stratix/n_cntr
sim/stratix/scale_cntr
sim/stratix/stratix_asynch_io
sim/stratix/stratix_asynch_lcell
sim/stratix/stratix_crcblock
sim/stratix/stratix_io
sim/stratix/stratix_io_register
sim/stratix/stratix_jtag
sim/stratix/stratix_lcell
sim/stratix/stratix_lcell_register
sim/stratix/stratix_lvds_receiver
sim/strat

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com