文件名称:src_100_power_tips_book
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- 上传时间:2012-11-16
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文件大小:1.76mb
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100 POWER TIPS FOR DESIGN FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
src_book/
src_book/13.14.15.coding/
src_book/13.14.15.coding/rtl/
src_book/13.14.15.coding/rtl/coding_style.v
src_book/13.14.15.coding/rtl/simple.v
src_book/13.14.15.coding/rtl/synth_support.v
src_book/13.14.15.coding/rtl/tb.v
src_book/13.14.15.coding/synth/
src_book/13.14.15.coding/synth/isim.cmd
src_book/13.14.15.coding/synth/sim1.wcfg
src_book/13.14.15.coding/synth/sim2.wcfg
src_book/13.14.15.coding/synth/synth.xise
src_book/13.14.15.coding/synth/synth_support.lso
src_book/16.inference/
src_book/16.inference/rtl/
src_book/16.inference/rtl/inference.v
src_book/16.inference/synth/
src_book/16.inference/synth/inference.lso
src_book/16.inference/synth/inference.ptwx
src_book/16.inference/synth/inference.stx
src_book/16.inference/synth/inference.unroutes
src_book/16.inference/synth/inference.xpi
src_book/16.inference/synth/inference_map.mrp
src_book/16.inference/synth/netgen/
src_book/16.inference/synth/netgen/map/
src_book/16.inference/synth/netgen/map/inference_map.sdf
src_book/16.inference/synth/netgen/map/inference_map.v
src_book/16.inference/synth/netgen/synthesis/
src_book/16.inference/synth/netgen/synthesis/inference_synthesis.v
src_book/16.inference/synth/synth.xise
src_book/17.mixed_verilog_vhdl/
src_book/17.mixed_verilog_vhdl/rtl/
src_book/17.mixed_verilog_vhdl/rtl/counter.vhd
src_book/17.mixed_verilog_vhdl/rtl/tb.v
src_book/17.mixed_verilog_vhdl/rtl/top.v
src_book/17.mixed_verilog_vhdl/synth/
src_book/17.mixed_verilog_vhdl/synth/isim.cmd
src_book/17.mixed_verilog_vhdl/synth/synth.xise
src_book/17.mixed_verilog_vhdl/synth/top.lso
src_book/17.mixed_verilog_vhdl/synth/top.ptwx
src_book/17.mixed_verilog_vhdl/synth/top.stx
src_book/17.mixed_verilog_vhdl/synth/top_map.mrp
src_book/18.verilog/
src_book/18.verilog/rtl/
src_book/18.verilog/rtl/verilog2001.v
src_book/18.verilog/synth/
src_book/18.verilog/synth/synth.xise
src_book/18.verilog/synth/verilog2001.lso
src_book/18.verilog/synth/verilog2001.stx
src_book/18.verilog/synth/verilog2001_map.mrp
src_book/20.21.clocking/
src_book/20.21.clocking/cores/
src_book/20.21.clocking/cores/.lso
src_book/20.21.clocking/cores/blk_mem.v
src_book/20.21.clocking/cores/blk_mem.xco
src_book/20.21.clocking/cores/clka_mmcm.v
src_book/20.21.clocking/cores/clka_mmcm.xco
src_book/20.21.clocking/cores/clk_dcm.v
src_book/20.21.clocking/cores/clk_dcm.xco
src_book/20.21.clocking/cores/clk_mmcm.v
src_book/20.21.clocking/cores/clk_mmcm.xco
src_book/20.21.clocking/cores/coregen.cgp
src_book/20.21.clocking/rtl/
src_book/20.21.clocking/rtl/clock_dcm.v
src_book/20.21.clocking/rtl/clock_inference.v
src_book/20.21.clocking/rtl/clock_mmcm.v
src_book/20.21.clocking/rtl/clock_schemes.v
src_book/20.21.clocking/rtl/timing_analyzer.v
src_book/20.21.clocking/synth/
src_book/20.21.clocking/synth/clock_dcm.lso
src_book/20.21.clocking/synth/clock_dcm.ptwx
src_book/20.21.clocking/synth/clock_dcm.stx
src_book/20.21.clocking/synth/clock_dcm.ucf
src_book/20.21.clocking/synth/clock_dcm.unroutes
src_book/20.21.clocking/synth/clock_dcm.xpi
src_book/20.21.clocking/synth/clock_dcm_map.mrp
src_book/20.21.clocking/synth/clock_inference.ptwx
src_book/20.21.clocking/synth/clock_inference.ucf
src_book/20.21.clocking/synth/clock_inference.unroutes
src_book/20.21.clocking/synth/clock_inference.xpi
src_book/20.21.clocking/synth/clock_inference_map.mrp
src_book/20.21.clocking/synth/clock_mmcm.clk_rgn
src_book/20.21.clocking/synth/clock_mmcm.dly
src_book/20.21.clocking/synth/clock_mmcm.lso
src_book/20.21.clocking/synth/clock_mmcm.ptwx
src_book/20.21.clocking/synth/clock_mmcm.pwr
src_book/20.21.clocking/synth/clock_mmcm.stx
src_book/20.21.clocking/synth/clock_mmcm.unroutes
src_book/20.21.clocking/synth/clock_mmcm.xpi
src_book/20.21.clocking/synth/clock_mmcm_map.mrp
src_book/20.21.clocking/synth/netgen/
src_book/20.21.clocking/synth/netgen/par/
src_book/20.21.clocking/synth/netgen/par/clock_mmcm_timesim.sdf
src_book/20.21.clocking/synth/netgen/par/clock_mmcm_timesim.v
src_book/20.21.clocking/synth/planAhead_run_1/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/constrs_1/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/runs/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/sources_1/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/wt/
src_book/20.21.clocking/synth/planAhead_run_1/synth.ppr
src_book/20.21.clocking/synth/synth.xise
src_book/20.21.clocking/synth/timing_analyzer.ptwx
src_book/20.21.clocking/synth/timing_analyzer.ucf
src_book/20.21.clocking/synth/timing_analyzer.unroutes
src_book/20.21.clocking/synth/timing_analyzer.xpi
src_book/20.21.clocking/synth/timing_analyzer_map.mrp
src_book/22.cdc/
src_book/22.cdc/rtl/
src_book/22.cdc/rtl/cdc.v
src_book/22.cdc/synth/
src_book/22.cdc/synth/cdc.lso
src_book/22.cdc/synth/cdc.ptwx
src_book/22.cdc/synth/cdc.stx
src_book/22.cdc/synth/cdc.tsi
src_book/22.cdc/synth/cdc.ucf
src_book/22.cdc/synth/cdc.unroutes
src_book/22.cdc/synth/cdc.xpi
src_book/22.cdc/synth/cdc_map.mrp
src_book/22.cdc/synth/synth.xise
src_book/23.synchronizers/
src_book/23.synchronizers/rtl/
src_book/23.synchronizers/rtl/cdc.v
src_b
src_book/13.14.15.coding/
src_book/13.14.15.coding/rtl/
src_book/13.14.15.coding/rtl/coding_style.v
src_book/13.14.15.coding/rtl/simple.v
src_book/13.14.15.coding/rtl/synth_support.v
src_book/13.14.15.coding/rtl/tb.v
src_book/13.14.15.coding/synth/
src_book/13.14.15.coding/synth/isim.cmd
src_book/13.14.15.coding/synth/sim1.wcfg
src_book/13.14.15.coding/synth/sim2.wcfg
src_book/13.14.15.coding/synth/synth.xise
src_book/13.14.15.coding/synth/synth_support.lso
src_book/16.inference/
src_book/16.inference/rtl/
src_book/16.inference/rtl/inference.v
src_book/16.inference/synth/
src_book/16.inference/synth/inference.lso
src_book/16.inference/synth/inference.ptwx
src_book/16.inference/synth/inference.stx
src_book/16.inference/synth/inference.unroutes
src_book/16.inference/synth/inference.xpi
src_book/16.inference/synth/inference_map.mrp
src_book/16.inference/synth/netgen/
src_book/16.inference/synth/netgen/map/
src_book/16.inference/synth/netgen/map/inference_map.sdf
src_book/16.inference/synth/netgen/map/inference_map.v
src_book/16.inference/synth/netgen/synthesis/
src_book/16.inference/synth/netgen/synthesis/inference_synthesis.v
src_book/16.inference/synth/synth.xise
src_book/17.mixed_verilog_vhdl/
src_book/17.mixed_verilog_vhdl/rtl/
src_book/17.mixed_verilog_vhdl/rtl/counter.vhd
src_book/17.mixed_verilog_vhdl/rtl/tb.v
src_book/17.mixed_verilog_vhdl/rtl/top.v
src_book/17.mixed_verilog_vhdl/synth/
src_book/17.mixed_verilog_vhdl/synth/isim.cmd
src_book/17.mixed_verilog_vhdl/synth/synth.xise
src_book/17.mixed_verilog_vhdl/synth/top.lso
src_book/17.mixed_verilog_vhdl/synth/top.ptwx
src_book/17.mixed_verilog_vhdl/synth/top.stx
src_book/17.mixed_verilog_vhdl/synth/top_map.mrp
src_book/18.verilog/
src_book/18.verilog/rtl/
src_book/18.verilog/rtl/verilog2001.v
src_book/18.verilog/synth/
src_book/18.verilog/synth/synth.xise
src_book/18.verilog/synth/verilog2001.lso
src_book/18.verilog/synth/verilog2001.stx
src_book/18.verilog/synth/verilog2001_map.mrp
src_book/20.21.clocking/
src_book/20.21.clocking/cores/
src_book/20.21.clocking/cores/.lso
src_book/20.21.clocking/cores/blk_mem.v
src_book/20.21.clocking/cores/blk_mem.xco
src_book/20.21.clocking/cores/clka_mmcm.v
src_book/20.21.clocking/cores/clka_mmcm.xco
src_book/20.21.clocking/cores/clk_dcm.v
src_book/20.21.clocking/cores/clk_dcm.xco
src_book/20.21.clocking/cores/clk_mmcm.v
src_book/20.21.clocking/cores/clk_mmcm.xco
src_book/20.21.clocking/cores/coregen.cgp
src_book/20.21.clocking/rtl/
src_book/20.21.clocking/rtl/clock_dcm.v
src_book/20.21.clocking/rtl/clock_inference.v
src_book/20.21.clocking/rtl/clock_mmcm.v
src_book/20.21.clocking/rtl/clock_schemes.v
src_book/20.21.clocking/rtl/timing_analyzer.v
src_book/20.21.clocking/synth/
src_book/20.21.clocking/synth/clock_dcm.lso
src_book/20.21.clocking/synth/clock_dcm.ptwx
src_book/20.21.clocking/synth/clock_dcm.stx
src_book/20.21.clocking/synth/clock_dcm.ucf
src_book/20.21.clocking/synth/clock_dcm.unroutes
src_book/20.21.clocking/synth/clock_dcm.xpi
src_book/20.21.clocking/synth/clock_dcm_map.mrp
src_book/20.21.clocking/synth/clock_inference.ptwx
src_book/20.21.clocking/synth/clock_inference.ucf
src_book/20.21.clocking/synth/clock_inference.unroutes
src_book/20.21.clocking/synth/clock_inference.xpi
src_book/20.21.clocking/synth/clock_inference_map.mrp
src_book/20.21.clocking/synth/clock_mmcm.clk_rgn
src_book/20.21.clocking/synth/clock_mmcm.dly
src_book/20.21.clocking/synth/clock_mmcm.lso
src_book/20.21.clocking/synth/clock_mmcm.ptwx
src_book/20.21.clocking/synth/clock_mmcm.pwr
src_book/20.21.clocking/synth/clock_mmcm.stx
src_book/20.21.clocking/synth/clock_mmcm.unroutes
src_book/20.21.clocking/synth/clock_mmcm.xpi
src_book/20.21.clocking/synth/clock_mmcm_map.mrp
src_book/20.21.clocking/synth/netgen/
src_book/20.21.clocking/synth/netgen/par/
src_book/20.21.clocking/synth/netgen/par/clock_mmcm_timesim.sdf
src_book/20.21.clocking/synth/netgen/par/clock_mmcm_timesim.v
src_book/20.21.clocking/synth/planAhead_run_1/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/constrs_1/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/runs/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/sources_1/
src_book/20.21.clocking/synth/planAhead_run_1/synth.data/wt/
src_book/20.21.clocking/synth/planAhead_run_1/synth.ppr
src_book/20.21.clocking/synth/synth.xise
src_book/20.21.clocking/synth/timing_analyzer.ptwx
src_book/20.21.clocking/synth/timing_analyzer.ucf
src_book/20.21.clocking/synth/timing_analyzer.unroutes
src_book/20.21.clocking/synth/timing_analyzer.xpi
src_book/20.21.clocking/synth/timing_analyzer_map.mrp
src_book/22.cdc/
src_book/22.cdc/rtl/
src_book/22.cdc/rtl/cdc.v
src_book/22.cdc/synth/
src_book/22.cdc/synth/cdc.lso
src_book/22.cdc/synth/cdc.ptwx
src_book/22.cdc/synth/cdc.stx
src_book/22.cdc/synth/cdc.tsi
src_book/22.cdc/synth/cdc.ucf
src_book/22.cdc/synth/cdc.unroutes
src_book/22.cdc/synth/cdc.xpi
src_book/22.cdc/synth/cdc_map.mrp
src_book/22.cdc/synth/synth.xise
src_book/23.synchronizers/
src_book/23.synchronizers/rtl/
src_book/23.synchronizers/rtl/cdc.v
src_b
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