文件名称:EasyFPGA030-
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- 上传时间:2012-11-16
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文件大小:235.92kb
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用EasyFPGA030开发板来实现串口通信接口,通过电脑端发送相应的数据,可以控制板上的LED灯和特定端口电平的变化。 -With EasyFPGA030 development board to implement serial communication interface, through the computer sends the appropriate data, the control panel LED lamp and a specific port-level changes.
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下载文件列表
asyn/asyn.prj
asyn/designer/impl1/async.adb
asyn/designer/impl1/async.dtf/verify.log
asyn/designer/impl1/async.ide_des
asyn/designer/impl1/async.pdb
asyn/designer/impl1/async.pdb.depends
asyn/designer/impl1/async.tcl
asyn/designer/impl1/async_fp/$$FlashPro_FPBBALTLPT1.L$$
asyn/designer/impl1/async_fp/async.log
asyn/designer/impl1/async_fp/async.pro
asyn/designer/impl1/async_fp/projectData/async.pdb
asyn/designer/impl1/async_receiver.ide_des
asyn/designer/impl1/async_transmitter.ide_des
asyn/designer/impl1/designer.log
asyn/hdl/async.v
asyn/hdl/async_receiver.v
asyn/hdl/async_transmitter.v
asyn/simulation/modelsim.ini
asyn/smartgen/smartgen.aws
asyn/synthesis/.recordref
asyn/synthesis/async.areasrr
asyn/synthesis/async.edn
asyn/synthesis/async.map
asyn/synthesis/async.pdc
asyn/synthesis/async.sdf
asyn/synthesis/async.so
asyn/synthesis/async.srd
asyn/synthesis/async.srm
asyn/synthesis/async.srr
asyn/synthesis/async.srs
asyn/synthesis/async.szr
asyn/synthesis/async.tlg
asyn/synthesis/async_sdc.sdc
asyn/synthesis/async_syn.prj
asyn/synthesis/run_options.txt
asyn/synthesis/stdout.log
asyn/synthesis/syntmp/async.plg
asyn/synthesis/traplog.tlg
asyn/viewdraw/vf/project.lst
asyn/viewdraw/viewdraw.ini
asyn/designer/impl1/async_fp/projectData
asyn/designer/impl1/async.dtf
asyn/designer/impl1/async_fp
asyn/designer/impl1/simulation
asyn/designer/impl1
asyn/synthesis/backup
asyn/synthesis/coreip
asyn/synthesis/syntmp
asyn/viewdraw/sch
asyn/viewdraw/sym
asyn/viewdraw/vf
asyn/viewdraw/wir
asyn/component
asyn/constraint
asyn/coreconsole
asyn/designer
asyn/hdl
asyn/phy_synthesis
asyn/simulation
asyn/smartgen
asyn/stimulus
asyn/synthesis
asyn/viewdraw
asyn
asyn/designer/impl1/async.adb
asyn/designer/impl1/async.dtf/verify.log
asyn/designer/impl1/async.ide_des
asyn/designer/impl1/async.pdb
asyn/designer/impl1/async.pdb.depends
asyn/designer/impl1/async.tcl
asyn/designer/impl1/async_fp/$$FlashPro_FPBBALTLPT1.L$$
asyn/designer/impl1/async_fp/async.log
asyn/designer/impl1/async_fp/async.pro
asyn/designer/impl1/async_fp/projectData/async.pdb
asyn/designer/impl1/async_receiver.ide_des
asyn/designer/impl1/async_transmitter.ide_des
asyn/designer/impl1/designer.log
asyn/hdl/async.v
asyn/hdl/async_receiver.v
asyn/hdl/async_transmitter.v
asyn/simulation/modelsim.ini
asyn/smartgen/smartgen.aws
asyn/synthesis/.recordref
asyn/synthesis/async.areasrr
asyn/synthesis/async.edn
asyn/synthesis/async.map
asyn/synthesis/async.pdc
asyn/synthesis/async.sdf
asyn/synthesis/async.so
asyn/synthesis/async.srd
asyn/synthesis/async.srm
asyn/synthesis/async.srr
asyn/synthesis/async.srs
asyn/synthesis/async.szr
asyn/synthesis/async.tlg
asyn/synthesis/async_sdc.sdc
asyn/synthesis/async_syn.prj
asyn/synthesis/run_options.txt
asyn/synthesis/stdout.log
asyn/synthesis/syntmp/async.plg
asyn/synthesis/traplog.tlg
asyn/viewdraw/vf/project.lst
asyn/viewdraw/viewdraw.ini
asyn/designer/impl1/async_fp/projectData
asyn/designer/impl1/async.dtf
asyn/designer/impl1/async_fp
asyn/designer/impl1/simulation
asyn/designer/impl1
asyn/synthesis/backup
asyn/synthesis/coreip
asyn/synthesis/syntmp
asyn/viewdraw/sch
asyn/viewdraw/sym
asyn/viewdraw/vf
asyn/viewdraw/wir
asyn/component
asyn/constraint
asyn/coreconsole
asyn/designer
asyn/hdl
asyn/phy_synthesis
asyn/simulation
asyn/smartgen
asyn/stimulus
asyn/synthesis
asyn/viewdraw
asyn
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