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文件名称:simple_spi

  • 所属分类：
    串口编程
  • 标签属性：
    [PDF]
  • 上传时间：
    2008-10-13
  • 文件大小：
    462.01kb
  • 已下载：
    0次
  • 提 供 者：
    J*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！

The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.



FEATURES:



·　　Compatible with Motorola’s SPI specifications

·　　Enhanced M68HC11 Serial Peripheral Interface

·　　4 entries deep read FIFO

·　　4 entries deep write FIFO

·　　Interrupt generation after 1, 2, 3, or 4 transferred bytes

·　　8 bit WISHBONE RevB.3 Classic interface

·　　Operates from a wide range of input clock frequencies

·　　Static synchronous design

·　　Fully synthesizable

-a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
(系统自动生成,下载前可以参看下载内容)

下载文件列表

simple_spi/CVS/Root
simple_spi/CVS/Repository
simple_spi/CVS/Entries
simple_spi/CVS
simple_spi/bench/CVS/Root
simple_spi/bench/CVS/Repository
simple_spi/bench/CVS/Entries
simple_spi/bench/CVS
simple_spi/bench/verilog/CVS/Root
simple_spi/bench/verilog/CVS/Repository
simple_spi/bench/verilog/CVS/Entries
simple_spi/bench/verilog/CVS
simple_spi/bench/verilog/spi_slave_model.v
simple_spi/bench/verilog/tst_bench_top.v
simple_spi/bench/verilog/wb_master_model.v
simple_spi/bench/verilog
simple_spi/bench
simple_spi/doc/CVS/Root
simple_spi/doc/CVS/Repository
simple_spi/doc/CVS/Entries
simple_spi/doc/CVS
simple_spi/doc/simple_spi.pdf
simple_spi/doc/src/CVS/Root
simple_spi/doc/src/CVS/Repository
simple_spi/doc/src/CVS/Entries
simple_spi/doc/src/CVS
simple_spi/doc/src/simple_spi.doc
simple_spi/doc/src
simple_spi/doc
simple_spi/rtl/CVS/Root
simple_spi/rtl/CVS/Repository
simple_spi/rtl/CVS/Entries
simple_spi/rtl/CVS
simple_spi/rtl/verilog/CVS/Root
simple_spi/rtl/verilog/CVS/Repository
simple_spi/rtl/verilog/CVS/Entries
simple_spi/rtl/verilog/CVS
simple_spi/rtl/verilog/fifo4.v
simple_spi/rtl/verilog/simple_spi_top.v
simple_spi/rtl/verilog
simple_spi/rtl
simple_spi/sim/CVS/Root
simple_spi/sim/CVS/Repository
simple_spi/sim/CVS/Entries
simple_spi/sim/CVS
simple_spi/sim/rtl_sim/CVS/Root
simple_spi/sim/rtl_sim/CVS/Repository
simple_spi/sim/rtl_sim/CVS/Entries
simple_spi/sim/rtl_sim/CVS
simple_spi/sim/rtl_sim/bin/CVS/Root
simple_spi/sim/rtl_sim/bin/CVS/Repository
simple_spi/sim/rtl_sim/bin/CVS/Entries
simple_spi/sim/rtl_sim/bin/CVS
simple_spi/sim/rtl_sim/bin/Makefile
simple_spi/sim/rtl_sim/bin
simple_spi/sim/rtl_sim/run/CVS/Root
simple_spi/sim/rtl_sim/run/CVS/Repository
simple_spi/sim/rtl_sim/run/CVS/Entries
simple_spi/sim/rtl_sim/run/CVS
simple_spi/sim/rtl_sim/run/Makefile
simple_spi/sim/rtl_sim/run/ncsim.log
simple_spi/sim/rtl_sim/run/ncvlog.log
simple_spi/sim/rtl_sim/run/simvision.sv
simple_spi/sim/rtl_sim/run/stdout.log
simple_spi/sim/rtl_sim/run/ncwork/CVS/Root
simple_spi/sim/rtl_sim/run/ncwork/CVS/Repository
simple_spi/sim/rtl_sim/run/ncwork/CVS/Entries
simple_spi/sim/rtl_sim/run/ncwork/CVS
simple_spi/sim/rtl_sim/run/ncwork/cds.lib
simple_spi/sim/rtl_sim/run/ncwork/hdl.var
simple_spi/sim/rtl_sim/run/ncwork/work/CVS/Root
simple_spi/sim/rtl_sim/run/ncwork/work/CVS/Repository
simple_spi/sim/rtl_sim/run/ncwork/work/CVS/Entries
simple_spi/sim/rtl_sim/run/ncwork/work/CVS
simple_spi/sim/rtl_sim/run/ncwork/work/.cdsvmod
simple_spi/sim/rtl_sim/run/ncwork/work/.inca.db.135.linux
simple_spi/sim/rtl_sim/run/ncwork/work/.inca.db.148.lnx86
simple_spi/sim/rtl_sim/run/ncwork/work/inca.linux.135.pak
simple_spi/sim/rtl_sim/run/ncwork/work/inca.lnx86.148.pak
simple_spi/sim/rtl_sim/run/ncwork/work
simple_spi/sim/rtl_sim/run/ncwork
simple_spi/sim/rtl_sim/run/waves/CVS/Root
simple_spi/sim/rtl_sim/run/waves/CVS/Repository
simple_spi/sim/rtl_sim/run/waves/CVS/Entries
simple_spi/sim/rtl_sim/run/waves/CVS
simple_spi/sim/rtl_sim/run/waves/waves.do
simple_spi/sim/rtl_sim/run/waves
simple_spi/sim/rtl_sim/run
simple_spi/sim/rtl_sim
simple_spi/sim
simple_spi
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