文件名称:design217
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在quartus II中实现的一段分频代码,具有很好的使用价值,希望大家能够更好的借鉴。-FW FWKPJF F WJL FW FEL,M FW,M GERWELJ GEW RMGLEJWR4E GER ER FL OFE RGFE GRE GRTE GTRE 4ER OT EWWQO .
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下载文件列表
design217/clk_div.bsf
design217/clk_div.v
design217/clk_div.v.bak
design217/COUNT4.bsf
design217/design.asm.rpt
design217/design.bdf
design217/design.done
design217/design.eda.rpt
design217/design.fit.rpt
design217/design.fit.smsg
design217/design.fit.summary
design217/design.flow.rpt
design217/design.map.rpt
design217/design.map.summary
design217/design.pin
design217/design.pof
design217/design.qpf
design217/design.qsf
design217/design.qws
design217/design.sof
design217/design.tan.rpt
design217/design.v.bak
design217/design_nativelink_simulation.rpt
design217/plusegen.bsf
design217/plusegen.v
design217/plusegen.v.bak
design217/simulation/modelsim/design.sft
design217/simulation/modelsim/design.vo
design217/simulation/modelsim/design.vt
design217/simulation/modelsim/design_modelsim.xrf
design217/simulation/modelsim/design_run_msim_rtl_verilog.do
design217/simulation/modelsim/design_run_msim_rtl_verilog.do.bak
design217/simulation/modelsim/design_v.sdo
design217/simulation/modelsim/modelsim.ini
design217/simulation/modelsim/msim_transcript
design217/simulation/modelsim/rtl_work/_info
design217/simulation/modelsim/rtl_work/_vmake
design217/simulation/modelsim/rtl_work/_temp/vlog1t1sjw
design217/simulation/modelsim/rtl_work/_temp/vlog76kevr
design217/simulation/modelsim/rtl_work/plusegen/verilog.prw
design217/simulation/modelsim/rtl_work/plusegen/verilog.psm
design217/simulation/modelsim/rtl_work/plusegen/_primary.dat
design217/simulation/modelsim/rtl_work/plusegen/_primary.dbs
design217/simulation/modelsim/rtl_work/plusegen/_primary.vhd
design217/simulation/modelsim/rtl_work/clk_div/verilog.prw
design217/simulation/modelsim/rtl_work/clk_div/verilog.psm
design217/simulation/modelsim/rtl_work/clk_div/_primary.dat
design217/simulation/modelsim/rtl_work/clk_div/_primary.dbs
design217/simulation/modelsim/rtl_work/clk_div/_primary.vhd
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/verilog.prw
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/verilog.psm
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/_primary.dat
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/_primary.dbs
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/_primary.vhd
design217/incremental_db/README
design217/incremental_db/compiled_partitions/design.root_partition.cmp.cdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.dfp
design217/incremental_db/compiled_partitions/design.root_partition.cmp.hdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.kpt
design217/incremental_db/compiled_partitions/design.root_partition.cmp.logdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.rcfdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.re.rcfdb
design217/incremental_db/compiled_partitions/design.root_partition.map.cdb
design217/incremental_db/compiled_partitions/design.root_partition.map.dpi
design217/incremental_db/compiled_partitions/design.root_partition.map.hdb
design217/incremental_db/compiled_partitions/design.root_partition.map.kpt
design217/db/design.(0).cnf.cdb
design217/db/design.(0).cnf.hdb
design217/db/design.(1).cnf.cdb
design217/db/design.(1).cnf.hdb
design217/db/design.(2).cnf.cdb
design217/db/design.(2).cnf.hdb
design217/db/design.(3).cnf.cdb
design217/db/design.(3).cnf.hdb
design217/db/design.asm.qmsg
design217/db/design.asm.rdb
design217/db/design.asm_labs.ddb
design217/db/design.cbx.xml
design217/db/design.cmp.bpm
design217/db/design.cmp.cdb
design217/db/design.cmp.ecobp
design217/db/design.cmp.hdb
design217/db/design.cmp.kpt
design217/db/design.cmp.logdb
design217/db/design.cmp.rdb
design217/db/design.cmp.tdb
design217/db/design.cmp0.ddb
design217/db/design.cmp2.ddb
design217/db/design.cmp_merge.kpt
design217/db/design.db_info
design217/db/design.eco.cdb
design217/db/design.eda.qmsg
design217/db/design.fit.qmsg
design217/db/design.hier_info
design217/db/design.hif
design217/db/design.lpc.html
design217/db/design.lpc.rdb
design217/db/design.lpc.txt
design217/db/design.map.bpm
design217/db/design.map.cdb
design217/db/design.map.ecobp
design217/db/design.map.hdb
design217/db/design.map.kpt
design217/db/design.map.logdb
design217/db/design.map.qmsg
design217/db/design.map_bb.cdb
design217/db/design.map_bb.hdb
design217/db/design.map_bb.logdb
design217/db/design.pre_map.cdb
design217/db/design.pre_map.hdb
design217/db/design.rtlv.hdb
design217/db/design.rtlv_sg.cdb
design217/db/design.rtlv_sg_swap.cdb
design217/db/design.sgdiff.cdb
design217/db/design.sgdiff.hdb
design217/db/design.sld_design_entry.sci
design217/db/design.sld_design_entry_dsc.sci
design217/db/design.smart_action.txt
design217/db/design.syn_hier_info
design217/db/design.tan.qmsg
design217/db/design.tis_db_list.ddb
design217/db/logic_util_heursitic.dat
design217/db/prev_cmp_design.asm.qmsg
design217/db/prev_cmp_design.eda.qmsg
design217/db/prev_cmp_design.fit.qmsg
design217/db/prev_cmp_design.map.qmsg
design217/db/prev_cmp_design.qmsg
design217/db/prev_cmp_design.tan.qmsg
design217/simulation/modelsim/rtl_work/_temp
design217/simulation/modelsim/rtl_work/plusegen
design217/simulation/modelsim/rtl
design217/clk_div.v
design217/clk_div.v.bak
design217/COUNT4.bsf
design217/design.asm.rpt
design217/design.bdf
design217/design.done
design217/design.eda.rpt
design217/design.fit.rpt
design217/design.fit.smsg
design217/design.fit.summary
design217/design.flow.rpt
design217/design.map.rpt
design217/design.map.summary
design217/design.pin
design217/design.pof
design217/design.qpf
design217/design.qsf
design217/design.qws
design217/design.sof
design217/design.tan.rpt
design217/design.v.bak
design217/design_nativelink_simulation.rpt
design217/plusegen.bsf
design217/plusegen.v
design217/plusegen.v.bak
design217/simulation/modelsim/design.sft
design217/simulation/modelsim/design.vo
design217/simulation/modelsim/design.vt
design217/simulation/modelsim/design_modelsim.xrf
design217/simulation/modelsim/design_run_msim_rtl_verilog.do
design217/simulation/modelsim/design_run_msim_rtl_verilog.do.bak
design217/simulation/modelsim/design_v.sdo
design217/simulation/modelsim/modelsim.ini
design217/simulation/modelsim/msim_transcript
design217/simulation/modelsim/rtl_work/_info
design217/simulation/modelsim/rtl_work/_vmake
design217/simulation/modelsim/rtl_work/_temp/vlog1t1sjw
design217/simulation/modelsim/rtl_work/_temp/vlog76kevr
design217/simulation/modelsim/rtl_work/plusegen/verilog.prw
design217/simulation/modelsim/rtl_work/plusegen/verilog.psm
design217/simulation/modelsim/rtl_work/plusegen/_primary.dat
design217/simulation/modelsim/rtl_work/plusegen/_primary.dbs
design217/simulation/modelsim/rtl_work/plusegen/_primary.vhd
design217/simulation/modelsim/rtl_work/clk_div/verilog.prw
design217/simulation/modelsim/rtl_work/clk_div/verilog.psm
design217/simulation/modelsim/rtl_work/clk_div/_primary.dat
design217/simulation/modelsim/rtl_work/clk_div/_primary.dbs
design217/simulation/modelsim/rtl_work/clk_div/_primary.vhd
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/verilog.prw
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/verilog.psm
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/_primary.dat
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/_primary.dbs
design217/simulation/modelsim/rtl_work/@c@o@u@n@t4/_primary.vhd
design217/incremental_db/README
design217/incremental_db/compiled_partitions/design.root_partition.cmp.cdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.dfp
design217/incremental_db/compiled_partitions/design.root_partition.cmp.hdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.kpt
design217/incremental_db/compiled_partitions/design.root_partition.cmp.logdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.rcfdb
design217/incremental_db/compiled_partitions/design.root_partition.cmp.re.rcfdb
design217/incremental_db/compiled_partitions/design.root_partition.map.cdb
design217/incremental_db/compiled_partitions/design.root_partition.map.dpi
design217/incremental_db/compiled_partitions/design.root_partition.map.hdb
design217/incremental_db/compiled_partitions/design.root_partition.map.kpt
design217/db/design.(0).cnf.cdb
design217/db/design.(0).cnf.hdb
design217/db/design.(1).cnf.cdb
design217/db/design.(1).cnf.hdb
design217/db/design.(2).cnf.cdb
design217/db/design.(2).cnf.hdb
design217/db/design.(3).cnf.cdb
design217/db/design.(3).cnf.hdb
design217/db/design.asm.qmsg
design217/db/design.asm.rdb
design217/db/design.asm_labs.ddb
design217/db/design.cbx.xml
design217/db/design.cmp.bpm
design217/db/design.cmp.cdb
design217/db/design.cmp.ecobp
design217/db/design.cmp.hdb
design217/db/design.cmp.kpt
design217/db/design.cmp.logdb
design217/db/design.cmp.rdb
design217/db/design.cmp.tdb
design217/db/design.cmp0.ddb
design217/db/design.cmp2.ddb
design217/db/design.cmp_merge.kpt
design217/db/design.db_info
design217/db/design.eco.cdb
design217/db/design.eda.qmsg
design217/db/design.fit.qmsg
design217/db/design.hier_info
design217/db/design.hif
design217/db/design.lpc.html
design217/db/design.lpc.rdb
design217/db/design.lpc.txt
design217/db/design.map.bpm
design217/db/design.map.cdb
design217/db/design.map.ecobp
design217/db/design.map.hdb
design217/db/design.map.kpt
design217/db/design.map.logdb
design217/db/design.map.qmsg
design217/db/design.map_bb.cdb
design217/db/design.map_bb.hdb
design217/db/design.map_bb.logdb
design217/db/design.pre_map.cdb
design217/db/design.pre_map.hdb
design217/db/design.rtlv.hdb
design217/db/design.rtlv_sg.cdb
design217/db/design.rtlv_sg_swap.cdb
design217/db/design.sgdiff.cdb
design217/db/design.sgdiff.hdb
design217/db/design.sld_design_entry.sci
design217/db/design.sld_design_entry_dsc.sci
design217/db/design.smart_action.txt
design217/db/design.syn_hier_info
design217/db/design.tan.qmsg
design217/db/design.tis_db_list.ddb
design217/db/logic_util_heursitic.dat
design217/db/prev_cmp_design.asm.qmsg
design217/db/prev_cmp_design.eda.qmsg
design217/db/prev_cmp_design.fit.qmsg
design217/db/prev_cmp_design.map.qmsg
design217/db/prev_cmp_design.qmsg
design217/db/prev_cmp_design.tan.qmsg
design217/simulation/modelsim/rtl_work/_temp
design217/simulation/modelsim/rtl_work/plusegen
design217/simulation/modelsim/rtl
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