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文件名称:spi_driver_verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.77mb
  • 已下载：
    0次
  • 提 供 者：
    C***
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    无
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SPI控制器RTL级源码，实现标准SPI硬件接口-SPI controller RTL-level source code to achieve the standard SPI hardware interface
相关搜索： spi rtl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

spi/tags/asyst_2/rtl/verilog/spi_clgen.v
spi/tags/asyst_2/rtl/verilog/spi_defines.v
spi/tags/asyst_2/rtl/verilog/spi_shift.v
spi/tags/asyst_2/rtl/verilog/spi_top.v
spi/tags/asyst_2/rtl/verilog/timescale.v
spi/tags/asyst_3/rtl/verilog/spi_clgen.v
spi/tags/asyst_3/rtl/verilog/spi_defines.v
spi/tags/asyst_3/rtl/verilog/spi_shift.v
spi/tags/asyst_3/rtl/verilog/spi_top.v
spi/tags/asyst_3/rtl/verilog/timescale.v
spi/tags/initial/bench/verilog/spi_slave_model.v
spi/tags/initial/bench/verilog/tb_spi_top.v
spi/tags/initial/bench/verilog/wb_master_model.v
spi/tags/initial/doc/src/spi.doc
spi/tags/initial/rtl/verilog/spi_clgen.v
spi/tags/initial/rtl/verilog/spi_defines.v
spi/tags/initial/rtl/verilog/spi_shift.v
spi/tags/initial/rtl/verilog/spi_top.v
spi/tags/initial/rtl/verilog/timescale.v
spi/tags/initial/sim/run/sim
spi/tags/initial/sim/run/tcl.scr
spi/tags/rel_1/bench/verilog/spi_slave_model.v
spi/tags/rel_1/bench/verilog/tb_spi_top.v
spi/tags/rel_1/bench/verilog/wb_master_model.v
spi/tags/rel_1/doc/spi.pdf
spi/tags/rel_1/doc/src/spi.doc
spi/tags/rel_1/rtl/verilog/spi_clgen.v
spi/tags/rel_1/rtl/verilog/spi_defines.v
spi/tags/rel_1/rtl/verilog/spi_shift.v
spi/tags/rel_1/rtl/verilog/spi_top.v
spi/tags/rel_1/rtl/verilog/timescale.v
spi/tags/rel_1/sim/run/sim
spi/tags/rel_1/sim/run/tcl.scr
spi/tags/rel_2/bench/verilog/spi_slave_model.v
spi/tags/rel_2/bench/verilog/tb_spi_top.v
spi/tags/rel_2/bench/verilog/wb_master_model.v
spi/tags/rel_2/doc/spi.pdf
spi/tags/rel_2/doc/src/spi.doc
spi/tags/rel_2/rtl/verilog/spi_clgen.v
spi/tags/rel_2/rtl/verilog/spi_defines.v
spi/tags/rel_2/rtl/verilog/spi_shift.v
spi/tags/rel_2/rtl/verilog/spi_top.v
spi/tags/rel_2/rtl/verilog/timescale.v
spi/tags/rel_2/sim/run/sim
spi/tags/rel_2/sim/run/tcl.scr
spi/tags/rel_3/bench/verilog/spi_slave_model.v
spi/tags/rel_3/bench/verilog/tb_spi_top.v
spi/tags/rel_3/bench/verilog/wb_master_model.v
spi/tags/rel_3/doc/spi.pdf
spi/tags/rel_3/doc/src/spi.doc
spi/tags/rel_3/rtl/verilog/spi_clgen.v
spi/tags/rel_3/rtl/verilog/spi_defines.v
spi/tags/rel_3/rtl/verilog/spi_shift.v
spi/tags/rel_3/rtl/verilog/spi_top.v
spi/tags/rel_3/rtl/verilog/timescale.v
spi/tags/rel_3/sim/run/sim
spi/tags/rel_3/sim/run/tcl.scr
spi/tags/rel_4/bench/verilog/spi_slave_model.v
spi/tags/rel_4/bench/verilog/tb_spi_top.v
spi/tags/rel_4/bench/verilog/wb_master_model.v
spi/tags/rel_4/doc/spi.pdf
spi/tags/rel_4/doc/src/spi.doc
spi/tags/rel_4/rtl/verilog/spi_clgen.v
spi/tags/rel_4/rtl/verilog/spi_defines.v
spi/tags/rel_4/rtl/verilog/spi_shift.v
spi/tags/rel_4/rtl/verilog/spi_top.v
spi/tags/rel_4/rtl/verilog/timescale.v
spi/tags/rel_4/sim/run/sim
spi/tags/rel_4/sim/run/tcl.scr
spi/tags/rel_5/bench/verilog/spi_slave_model.v
spi/tags/rel_5/bench/verilog/tb_spi_top.v
spi/tags/rel_5/bench/verilog/wb_master_model.v
spi/tags/rel_5/doc/spi.pdf
spi/tags/rel_5/doc/src/spi.doc
spi/tags/rel_5/rtl/verilog/spi_clgen.v
spi/tags/rel_5/rtl/verilog/spi_defines.v
spi/tags/rel_5/rtl/verilog/spi_shift.v
spi/tags/rel_5/rtl/verilog/spi_top.v
spi/tags/rel_5/rtl/verilog/timescale.v
spi/tags/rel_5/sim/run/sim
spi/tags/rel_5/sim/run/tcl.scr
spi/tags/rel_6/bench/verilog/spi_slave_model.v
spi/tags/rel_6/bench/verilog/tb_spi_top.v
spi/tags/rel_6/bench/verilog/wb_master_model.v
spi/tags/rel_6/doc/spi.pdf
spi/tags/rel_6/doc/src/spi.doc
spi/tags/rel_6/rtl/verilog/spi_clgen.v
spi/tags/rel_6/rtl/verilog/spi_defines.v
spi/tags/rel_6/rtl/verilog/spi_shift.v
spi/tags/rel_6/rtl/verilog/spi_top.v
spi/tags/rel_6/rtl/verilog/timescale.v
spi/tags/rel_6/sim/run/sim
spi/tags/rel_6/sim/run/tcl.scr
spi/tags/rel_7/bench/verilog/spi_slave_model.v
spi/tags/rel_7/bench/verilog/tb_spi_top.v
spi/tags/rel_7/bench/verilog/wb_master_model.v
spi/tags/rel_7/doc/spi.pdf
spi/tags/rel_7/doc/src/spi.doc
spi/tags/rel_7/rtl/verilog/spi_clgen.v
spi/tags/rel_7/rtl/verilog/spi_defines.v
spi/tags/rel_7/rtl/verilog/spi_shift.v
spi/tags/rel_7/rtl/verilog/spi_top.v
spi/tags/rel_7/rtl/verilog/timescale.v
spi/tags/rel_7/sim/run/sim
spi/tags/rel_7/sim/run/tcl.scr
spi/tags/rel_8/bench/verilog/spi_slave_model.v
spi/tags/rel_8/bench/verilog/tb_spi_top.v
spi/tags/rel_8/bench/verilog/wb_master_model.v
spi/tags/rel_8/doc/spi.pdf
spi/tags/rel_8/doc/src/spi.doc
spi/tags/rel_8/rtl/verilog/spi_clgen.v
spi/tags/rel_8/rtl/verilog/spi_defines.v
spi/tags/rel_8/rtl/verilog/spi_shift.v
spi/tags/rel_8/rtl/verilog/spi_top.v
spi/tags/rel_8/rtl/verilog/timescale.v
spi/tags/rel_8/sim/rtl_sim/run/rtl.fl
spi/tags/rel_8/sim/rtl_sim/run/run_sim
spi/tags/rel_8/sim/rtl_sim/run/sim.fl
spi/trunk/bench/verilog/spi_slave_model.v
spi/trunk/bench/verilog/tb_spi_top.v
spi/trunk/bench/verilog/wb_master_model.v
spi/trunk/doc/spi.pdf
spi/trunk/doc/src/spi.doc
spi/trunk/rtl/verilog/spi_clgen.v
spi/trunk/rtl/verilog/spi_defines.v
spi/trunk/rtl/verilog/spi_shift.v
spi/trunk/rtl/verilog/spi_top.v
spi/trunk/rtl/verilog/timescale.v
spi/trunk/sim/rtl_sim/run/rtl.fl
spi/trunk/sim/rtl_sim/run/run_sim
spi/trunk/sim/rtl_sim/run/sim.fl
spi/tags/rel_8/sim/rtl_sim/run
spi/tags/asyst_2/rtl/verilog
spi/tags/asyst_3/rtl/verilog
spi/tags/initial/bench/verilog
spi/tags/initial/doc/src
spi/tags/initial/rtl/verilog
spi/tags/initial/sim/r

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