文件名称:DDR_SDRAM_Controller
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DDR RAM控制器的VHDL源码,实现平台是Lattice FPGA,功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
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下载文件列表
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/arrow.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/arrow1.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/ddr_controller.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/diskette.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/external.css
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/footer.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/go.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/header.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/make_agent_emb.jpg
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/pdfmid.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/ref_design_logo.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/spacer.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.htm
rd1020_DDR SDRAM Controller/rd1020.pdf
rd1020_DDR SDRAM Controller/source/ddr_ctrl.v
rd1020_DDR SDRAM Controller/source/ddr_data.v
rd1020_DDR SDRAM Controller/source/ddr_par.v
rd1020_DDR SDRAM Controller/source/ddr_pll_orca.v
rd1020_DDR SDRAM Controller/source/ddr_pll_orca_sp.v
rd1020_DDR SDRAM Controller/source/ddr_sig.v
rd1020_DDR SDRAM Controller/source/ddr_top.v
rd1020_DDR SDRAM Controller/testbench/ddr_tb.v
rd1020_DDR SDRAM Controller/testbench/stimulus.v
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files
rd1020_DDR SDRAM Controller/source
rd1020_DDR SDRAM Controller/testbench
rd1020_DDR SDRAM Controller
www.dssz.com.txt
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/arrow1.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/ddr_controller.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/diskette.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/external.css
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/footer.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/go.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/header.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/make_agent_emb.jpg
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/pdfmid.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/ref_design_logo.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/spacer.gif
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.htm
rd1020_DDR SDRAM Controller/rd1020.pdf
rd1020_DDR SDRAM Controller/source/ddr_ctrl.v
rd1020_DDR SDRAM Controller/source/ddr_data.v
rd1020_DDR SDRAM Controller/source/ddr_par.v
rd1020_DDR SDRAM Controller/source/ddr_pll_orca.v
rd1020_DDR SDRAM Controller/source/ddr_pll_orca_sp.v
rd1020_DDR SDRAM Controller/source/ddr_sig.v
rd1020_DDR SDRAM Controller/source/ddr_top.v
rd1020_DDR SDRAM Controller/testbench/ddr_tb.v
rd1020_DDR SDRAM Controller/testbench/stimulus.v
rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files
rd1020_DDR SDRAM Controller/source
rd1020_DDR SDRAM Controller/testbench
rd1020_DDR SDRAM Controller
www.dssz.com.txt
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