文件名称:VHDL-six
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用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
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下载文件列表
work1/devider.acf
work1/devider.vhd
work1/devider.hif
work1/devider.cnf
work1/DEVIDER.sym
work1/devider(1).cnf
work1/devider(2).cnf
work1/devider(3).cnf
work1/devider(4).cnf
work1/devider(5).cnf
work1/devider.pin
work1/devider.fit
work1/devider.ndb
work1/devider.snf
work1/devider.pof
work1/devider.scf
work1/devider.mmf
work1/U1909818.DLS
work1/U0262126.DLS
work1/U5700705.DLS
work1/LIB.DLS
work1/devider.rpt
work1
www.dssz.com.txt
work1/devider.vhd
work1/devider.hif
work1/devider.cnf
work1/DEVIDER.sym
work1/devider(1).cnf
work1/devider(2).cnf
work1/devider(3).cnf
work1/devider(4).cnf
work1/devider(5).cnf
work1/devider.pin
work1/devider.fit
work1/devider.ndb
work1/devider.snf
work1/devider.pof
work1/devider.scf
work1/devider.mmf
work1/U1909818.DLS
work1/U0262126.DLS
work1/U5700705.DLS
work1/LIB.DLS
work1/devider.rpt
work1
www.dssz.com.txt
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