文件名称:uart_wb
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- 上传时间:2012-11-16
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文件大小:192.35kb
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已下载:0次
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兼容wishbone bus的uart模块,方便用户修改,时候初学者学习-Compatible with wishbone bus the uart module, user-friendly changes beginners to learn when
相关搜索: uart wishbone
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下载文件列表
uart_wb/eval_params.v
uart_wb/rtl/intface.v
uart_wb/rtl/modem.v
uart_wb/rtl/pmi_fifo.v
uart_wb/rtl/rxcver.v
uart_wb/rtl/rxcver_fifo.v
uart_wb/rtl/txcver_fifo.v
uart_wb/rtl/txcver_fifo.v.bak
uart_wb/rtl/txmitt.v
uart_wb/rtl/uart_core.v
uart_wb/uart_core.xml
uart_wb/uart_core_tb.v
uart_wb/uart_core_tb.v.bak
uart_wb/uart_wb_tb.cr.mti
uart_wb/uart_wb_tb.mpf
uart_wb/vsim.wlf
uart_wb/work/intface/verilog.asm
uart_wb/work/intface/verilog.rw
uart_wb/work/intface/_primary.dat
uart_wb/work/intface/_primary.dbs
uart_wb/work/intface/_primary.vhd
uart_wb/work/modem/verilog.asm
uart_wb/work/modem/verilog.rw
uart_wb/work/modem/_primary.dat
uart_wb/work/modem/_primary.dbs
uart_wb/work/modem/_primary.vhd
uart_wb/work/pmi_fifo/_primary.dat
uart_wb/work/pmi_fifo/_primary.dbs
uart_wb/work/pmi_fifo/_primary.vhd
uart_wb/work/rxcver/verilog.asm
uart_wb/work/rxcver/verilog.rw
uart_wb/work/rxcver/_primary.dat
uart_wb/work/rxcver/_primary.dbs
uart_wb/work/rxcver/_primary.vhd
uart_wb/work/rxcver_fifo/_primary.dat
uart_wb/work/rxcver_fifo/_primary.dbs
uart_wb/work/rxcver_fifo/_primary.vhd
uart_wb/work/txcver_fifo/_primary.dat
uart_wb/work/txcver_fifo/_primary.dbs
uart_wb/work/txcver_fifo/_primary.vhd
uart_wb/work/txmitt/verilog.asm
uart_wb/work/txmitt/verilog.rw
uart_wb/work/txmitt/_primary.dat
uart_wb/work/txmitt/_primary.dbs
uart_wb/work/txmitt/_primary.vhd
uart_wb/work/uart_core/verilog.asm
uart_wb/work/uart_core/verilog.rw
uart_wb/work/uart_core/_primary.dat
uart_wb/work/uart_core/_primary.dbs
uart_wb/work/uart_core/_primary.vhd
uart_wb/work/uart_core_tb/verilog.asm
uart_wb/work/uart_core_tb/verilog.rw
uart_wb/work/uart_core_tb/_primary.dat
uart_wb/work/uart_core_tb/_primary.dbs
uart_wb/work/uart_core_tb/_primary.vhd
uart_wb/work/_info
uart_wb/work/_temp/vlog1y9r4r
uart_wb/work/_temp/vloga2g8vi
uart_wb/work/_temp/vloggg8rg4
uart_wb/work/_temp/vlogii3bnt
uart_wb/work/_temp/vlogkwd9bf
uart_wb/work/_temp/vlogq7btzf
uart_wb/work/_temp/vlogqbhfnr
uart_wb/work/_temp/vlogsw5614
uart_wb/work/_vmake
uart_wb/work/intface
uart_wb/work/modem
uart_wb/work/pmi_fifo
uart_wb/work/rxcver
uart_wb/work/rxcver_fifo
uart_wb/work/txcver_fifo
uart_wb/work/txmitt
uart_wb/work/uart_core
uart_wb/work/uart_core_tb
uart_wb/work/_temp
uart_wb/rtl
uart_wb/work
uart_wb
uart_wb/rtl/intface.v
uart_wb/rtl/modem.v
uart_wb/rtl/pmi_fifo.v
uart_wb/rtl/rxcver.v
uart_wb/rtl/rxcver_fifo.v
uart_wb/rtl/txcver_fifo.v
uart_wb/rtl/txcver_fifo.v.bak
uart_wb/rtl/txmitt.v
uart_wb/rtl/uart_core.v
uart_wb/uart_core.xml
uart_wb/uart_core_tb.v
uart_wb/uart_core_tb.v.bak
uart_wb/uart_wb_tb.cr.mti
uart_wb/uart_wb_tb.mpf
uart_wb/vsim.wlf
uart_wb/work/intface/verilog.asm
uart_wb/work/intface/verilog.rw
uart_wb/work/intface/_primary.dat
uart_wb/work/intface/_primary.dbs
uart_wb/work/intface/_primary.vhd
uart_wb/work/modem/verilog.asm
uart_wb/work/modem/verilog.rw
uart_wb/work/modem/_primary.dat
uart_wb/work/modem/_primary.dbs
uart_wb/work/modem/_primary.vhd
uart_wb/work/pmi_fifo/_primary.dat
uart_wb/work/pmi_fifo/_primary.dbs
uart_wb/work/pmi_fifo/_primary.vhd
uart_wb/work/rxcver/verilog.asm
uart_wb/work/rxcver/verilog.rw
uart_wb/work/rxcver/_primary.dat
uart_wb/work/rxcver/_primary.dbs
uart_wb/work/rxcver/_primary.vhd
uart_wb/work/rxcver_fifo/_primary.dat
uart_wb/work/rxcver_fifo/_primary.dbs
uart_wb/work/rxcver_fifo/_primary.vhd
uart_wb/work/txcver_fifo/_primary.dat
uart_wb/work/txcver_fifo/_primary.dbs
uart_wb/work/txcver_fifo/_primary.vhd
uart_wb/work/txmitt/verilog.asm
uart_wb/work/txmitt/verilog.rw
uart_wb/work/txmitt/_primary.dat
uart_wb/work/txmitt/_primary.dbs
uart_wb/work/txmitt/_primary.vhd
uart_wb/work/uart_core/verilog.asm
uart_wb/work/uart_core/verilog.rw
uart_wb/work/uart_core/_primary.dat
uart_wb/work/uart_core/_primary.dbs
uart_wb/work/uart_core/_primary.vhd
uart_wb/work/uart_core_tb/verilog.asm
uart_wb/work/uart_core_tb/verilog.rw
uart_wb/work/uart_core_tb/_primary.dat
uart_wb/work/uart_core_tb/_primary.dbs
uart_wb/work/uart_core_tb/_primary.vhd
uart_wb/work/_info
uart_wb/work/_temp/vlog1y9r4r
uart_wb/work/_temp/vloga2g8vi
uart_wb/work/_temp/vloggg8rg4
uart_wb/work/_temp/vlogii3bnt
uart_wb/work/_temp/vlogkwd9bf
uart_wb/work/_temp/vlogq7btzf
uart_wb/work/_temp/vlogqbhfnr
uart_wb/work/_temp/vlogsw5614
uart_wb/work/_vmake
uart_wb/work/intface
uart_wb/work/modem
uart_wb/work/pmi_fifo
uart_wb/work/rxcver
uart_wb/work/rxcver_fifo
uart_wb/work/txcver_fifo
uart_wb/work/txmitt
uart_wb/work/uart_core
uart_wb/work/uart_core_tb
uart_wb/work/_temp
uart_wb/rtl
uart_wb/work
uart_wb
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