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文件名称:74serie-code

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    2012-11-16
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    2.63mb
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74系列的源代码 里面还包含了testbench和详细的代码说明-Prepared by flash controller vhdL source code. Contains testbench. Programming Language:VHDL, Tags:VHDL-FPGA-Verilog,
(系统自动生成,下载前可以参看下载内容)

下载文件列表

exam/74138/74138.done
exam/74138/74138.flow.rpt
exam/74138/74138.map.rpt
exam/74138/74138.map.summary
exam/74138/74138.qsf
exam/74138/74138.v
exam/74138/74138.v.bak
exam/74138/74hc138.pdf
exam/74138/db/74138.(0).cnf.cdb
exam/74138/db/74138.(0).cnf.hdb
exam/74138/db/74138.cbx.xml
exam/74138/db/74138.cmp.rdb
exam/74138/db/74138.cmp_merge.kpt
exam/74138/db/74138.db_info
exam/74138/db/74138.hier_info
exam/74138/db/74138.hif
exam/74138/db/74138.lpc.html
exam/74138/db/74138.lpc.rdb
exam/74138/db/74138.lpc.txt
exam/74138/db/74138.map.bpm
exam/74138/db/74138.map.cdb
exam/74138/db/74138.map.hdb
exam/74138/db/74138.map.kpt
exam/74138/db/74138.map.logdb
exam/74138/db/74138.map.qmsg
exam/74138/db/74138.map_bb.cdb
exam/74138/db/74138.map_bb.hdb
exam/74138/db/74138.map_bb.logdb
exam/74138/db/74138.pre_map.cdb
exam/74138/db/74138.pre_map.hdb
exam/74138/db/74138.rpp.qmsg
exam/74138/db/74138.rtlv.hdb
exam/74138/db/74138.rtlv_sg.cdb
exam/74138/db/74138.rtlv_sg_swap.cdb
exam/74138/db/74138.sgate.rvd
exam/74138/db/74138.sgate_sm.rvd
exam/74138/db/74138.sgdiff.cdb
exam/74138/db/74138.sgdiff.hdb
exam/74138/db/74138.sld_design_entry.sci
exam/74138/db/74138.sld_design_entry_dsc.sci
exam/74138/db/74138.smart_action.txt
exam/74138/db/74138.syn_hier_info
exam/74138/db/74138.tis_db_list.ddb
exam/74138/db/74138.tmw_info
exam/74138/db/logic_util_heursitic.dat
exam/74138/db/prev_cmp_74138.qmsg
exam/74138/incremental_db/compiled_partitions/74138.db_info
exam/74138/incremental_db/compiled_partitions/74138.root_partition.map.cdb
exam/74138/incremental_db/compiled_partitions/74138.root_partition.map.dpi
exam/74138/incremental_db/compiled_partitions/74138.root_partition.map.hdb
exam/74138/incremental_db/compiled_partitions/74138.root_partition.map.kpt
exam/74138/incremental_db/README
exam/74138/run.do
exam/74138/s_74138.cr.mti
exam/74138/s_74138.mpf
exam/74138/s_74138.qpf
exam/74138/s_74138.xml
exam/74138/s_74138_tb.v
exam/74138/s_74138_tb.v.bak
exam/74138/vsim.wlf
exam/74138/work/s_74138/verilog.asm
exam/74138/work/s_74138/_primary.dat
exam/74138/work/s_74138/_primary.dbs
exam/74138/work/s_74138/_primary.vhd
exam/74138/work/s_74138_tb/verilog.asm
exam/74138/work/s_74138_tb/_primary.dat
exam/74138/work/s_74138_tb/_primary.dbs
exam/74138/work/s_74138_tb/_primary.vhd
exam/74138/work/_info
exam/74138/work/_opt/vopt2iexfg
exam/74138/work/_opt/vopt524tfg
exam/74138/work/_opt/vopt9isqfg
exam/74138/work/_opt/voptg13egg
exam/74138/work/_opt/voptg29gze
exam/74138/work/_opt/voptjhragg
exam/74138/work/_opt/voptkiydze
exam/74138/work/_opt/voptq2kaze
exam/74138/work/_opt/voptqkm7zd
exam/74138/work/_opt/voptyhx00f
exam/74138/work/_opt/_deps
exam/74138/work/_temp/vlog32g9ff
exam/74138/work/_temp/vlog3zcsfj
exam/74138/work/_temp/vlogc0a856
exam/74164/74hc164.pdf
exam/74164/db/logic_util_heursitic.dat
exam/74164/db/prev_cmp_s_74164.qmsg
exam/74164/db/s_74164.(0).cnf.cdb
exam/74164/db/s_74164.(0).cnf.hdb
exam/74164/db/s_74164.cbx.xml
exam/74164/db/s_74164.cmp.rdb
exam/74164/db/s_74164.cmp_merge.kpt
exam/74164/db/s_74164.db_info
exam/74164/db/s_74164.hier_info
exam/74164/db/s_74164.hif
exam/74164/db/s_74164.lpc.html
exam/74164/db/s_74164.lpc.rdb
exam/74164/db/s_74164.lpc.txt
exam/74164/db/s_74164.map.bpm
exam/74164/db/s_74164.map.cdb
exam/74164/db/s_74164.map.hdb
exam/74164/db/s_74164.map.kpt
exam/74164/db/s_74164.map.logdb
exam/74164/db/s_74164.map.qmsg
exam/74164/db/s_74164.map_bb.cdb
exam/74164/db/s_74164.map_bb.hdb
exam/74164/db/s_74164.map_bb.logdb
exam/74164/db/s_74164.pre_map.cdb
exam/74164/db/s_74164.pre_map.hdb
exam/74164/db/s_74164.rpp.qmsg
exam/74164/db/s_74164.rtlv.hdb
exam/74164/db/s_74164.rtlv_sg.cdb
exam/74164/db/s_74164.rtlv_sg_swap.cdb
exam/74164/db/s_74164.sgate.rvd
exam/74164/db/s_74164.sgate_sm.rvd
exam/74164/db/s_74164.sgdiff.cdb
exam/74164/db/s_74164.sgdiff.hdb
exam/74164/db/s_74164.sld_design_entry.sci
exam/74164/db/s_74164.sld_design_entry_dsc.sci
exam/74164/db/s_74164.smart_action.txt
exam/74164/db/s_74164.syn_hier_info
exam/74164/db/s_74164.tis_db_list.ddb
exam/74164/db/s_74164.tmw_info
exam/74164/incremental_db/compiled_partitions/s_74164.db_info
exam/74164/incremental_db/compiled_partitions/s_74164.root_partition.map.cdb
exam/74164/incremental_db/compiled_partitions/s_74164.root_partition.map.dpi
exam/74164/incremental_db/compiled_partitions/s_74164.root_partition.map.hdb
exam/74164/incremental_db/compiled_partitions/s_74164.root_partition.map.kpt
exam/74164/incremental_db/README
exam/74164/run.do
exam/74164/run.do.bak
exam/74164/s_74164.cr.mti
exam/74164/s_74164.done
exam/74164/s_74164.flow.rpt
exam/74164/s_74164.map.rpt
exam/74164/s_74164.map.summary
exam/74164/s_74164.mpf
exam/74164/s_74164.qpf
exam/74164/s_74164.qsf
exam/74164/s_74164.v
exam/74164/s_74164.v.bak
exam/74164/s_74164.xml
exam/74164/s_74164_tb.v
exam/74164/s_74164_tb.v.bak
exam/74164/vsim.wlf
exam/74164/work/s_74164/verilog.asm
exam/74164/work/s_74164/_primary.dat
exam/74164/work/s_74164/_primary.dbs
exam/74164/work/s_74164/_primary.vhd
exam/74164/work/s_74164_tb/verilog.asm
exam/74164/work/s_74164_tb/_primary.dat
exam/74164/work/s_74164_tb/_primary.dbs
exam/74164/work/s_74164_tb/_prim

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