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文件名称:SDRAM_RaW

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.05mb
  • 已下载：
    0次
  • 提 供 者：
    myn***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

本实例用于控制开发板上面的SDRAM完成读写功能；先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。-This instance is used to control the development board to complete the above SDRAM read and write capabilities　first SDRAM write data inside, and then compare the data read out, if you do not match on the adoption of LED lights show, if consistent, LED is not lit.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SDRAM_R&W/doc/micron_sdram.pdf
SDRAM_R&W/part1/part1_32/model/mt48lc2m32b2.v
SDRAM_R&W/part1/part1_32/rtl/Command.v
SDRAM_R&W/part1/part1_32/rtl/control_interface.v
SDRAM_R&W/part1/part1_32/rtl/Params.v
SDRAM_R&W/part1/part1_32/rtl/sdr_data_path.v
SDRAM_R&W/part1/part1_32/rtl/sdr_sdram.v
SDRAM_R&W/part1/part1_32/sim/Command.v
SDRAM_R&W/part1/part1_32/sim/control_interface.v
SDRAM_R&W/part1/part1_32/sim/mt48lc2m32b2.v
SDRAM_R&W/part1/part1_32/sim/Params.v
SDRAM_R&W/part1/part1_32/sim/sd32try.cr.mti
SDRAM_R&W/part1/part1_32/sim/sd32try.mpf
SDRAM_R&W/part1/part1_32/sim/sdram_test_tb.v
SDRAM_R&W/part1/part1_32/sim/sdr_data_path.v
SDRAM_R&W/part1/part1_32/sim/sdr_sdram.v
SDRAM_R&W/part1/part1_32/sim/sdtry.cr.mti
SDRAM_R&W/part1/part1_32/sim/vsim.wlf
SDRAM_R&W/part1/part1_32/sim/wave.do
SDRAM_R&W/part1/part1_32/sim/work/command/verilog.asm
SDRAM_R&W/part1/part1_32/sim/work/command/_primary.dat
SDRAM_R&W/part1/part1_32/sim/work/command/_primary.vhd
SDRAM_R&W/part1/part1_32/sim/work/control_interface/verilog.asm
SDRAM_R&W/part1/part1_32/sim/work/control_interface/_primary.dat
SDRAM_R&W/part1/part1_32/sim/work/control_interface/_primary.vhd
SDRAM_R&W/part1/part1_32/sim/work/mt48lc2m32b2/verilog.asm
SDRAM_R&W/part1/part1_32/sim/work/mt48lc2m32b2/_primary.dat
SDRAM_R&W/part1/part1_32/sim/work/mt48lc2m32b2/_primary.vhd
SDRAM_R&W/part1/part1_32/sim/work/sdram_test_tb/verilog.asm
SDRAM_R&W/part1/part1_32/sim/work/sdram_test_tb/_primary.dat
SDRAM_R&W/part1/part1_32/sim/work/sdram_test_tb/_primary.vhd
SDRAM_R&W/part1/part1_32/sim/work/sdr_data_path/verilog.asm
SDRAM_R&W/part1/part1_32/sim/work/sdr_data_path/_primary.dat
SDRAM_R&W/part1/part1_32/sim/work/sdr_data_path/_primary.vhd
SDRAM_R&W/part1/part1_32/sim/work/sdr_sdram/verilog.asm
SDRAM_R&W/part1/part1_32/sim/work/sdr_sdram/_primary.dat
SDRAM_R&W/part1/part1_32/sim/work/sdr_sdram/_primary.vhd
SDRAM_R&W/part1/part1_32/sim/work/_info
SDRAM_R&W/part1/part1_32/test_bench/sdram_test_tb.v
SDRAM_R&W/part1/part1_32/wave/32wave.bmp
SDRAM_R&W/part1/part2_16/model/mt48lc8m16a2.v
SDRAM_R&W/part1/part2_16/rtl/Command.v
SDRAM_R&W/part1/part2_16/rtl/control_interface.v
SDRAM_R&W/part1/part2_16/rtl/Params.v
SDRAM_R&W/part1/part2_16/rtl/sdr_data_path.v
SDRAM_R&W/part1/part2_16/rtl/sdr_sdram.v
SDRAM_R&W/part1/part2_16/sim/Command.v
SDRAM_R&W/part1/part2_16/sim/control_interface.v
SDRAM_R&W/part1/part2_16/sim/mt48lc8m16a2.v
SDRAM_R&W/part1/part2_16/sim/mt48lc8m16a2.v.bak
SDRAM_R&W/part1/part2_16/sim/Params.v
SDRAM_R&W/part1/part2_16/sim/Params.v.bak
SDRAM_R&W/part1/part2_16/sim/sdram_test_tb.v
SDRAM_R&W/part1/part2_16/sim/sdram_test_tb.v.bak
SDRAM_R&W/part1/part2_16/sim/sdr_data_path.v
SDRAM_R&W/part1/part2_16/sim/sdr_sdram.v
SDRAM_R&W/part1/part2_16/sim/sdr_sdram.v.bak
SDRAM_R&W/part1/part2_16/sim/sdtest.cr.mti
SDRAM_R&W/part1/part2_16/sim/sdtest.mpf
SDRAM_R&W/part1/part2_16/sim/vish_stacktrace.vstf
SDRAM_R&W/part1/part2_16/sim/vsim.wlf
SDRAM_R&W/part1/part2_16/sim/work/command/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/command/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/command/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/control_interface/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/control_interface/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/control_interface/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/mt48lc8m16a2/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/mt48lc8m16a2/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/mt48lc8m16a2/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/sdram_test/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/sdram_test/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/sdram_test/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/sdram_test_tb/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/sdram_test_tb/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/sdram_test_tb/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/sdr_data_path/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/sdr_data_path/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/sdr_data_path/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/sdr_sdram/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/sdr_sdram/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/sdr_sdram/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/test/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/test/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/test/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/test_top/verilog.asm
SDRAM_R&W/part1/part2_16/sim/work/test_top/_primary.dat
SDRAM_R&W/part1/part2_16/sim/work/test_top/_primary.vhd
SDRAM_R&W/part1/part2_16/sim/work/_info
SDRAM_R&W/part1/part2_16/test_bench/sdram_test_tb.v
SDRAM_R&W/part1/part2_16/test_bench/sdram_test_tb.v.bak
SDRAM_R&W/part1/part2_16/wave/wave.bmp
SDRAM_R&W/part2/dowload/test.bit
SDRAM_R&W/part2/dowload/test.mcs
SDRAM_R&W/part2/project/automake.log
SDRAM_R&W/part2/project/bitgen.ut
SDRAM_R&W/part2/project/Project.dhp
SDRAM_R&W/part2/project/project.ise
SDRAM_R&W/part2/project/project.ise_ISE_Backup
SDRAM_R&W/part2/project/test.bgn
SDRAM_R&W/part2/project/test.bit
SDRAM_R&W/part2/project/test.bld
SDRAM_R&W/part2/project/test.cmd_log
SDRAM_R&W/part2/project/test.drc
SDRAM_R&W/part2/project/test.lfp

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