文件名称:exp_micro_s
-
所属分类：
- 标签属性：
- 上传时间：2012-11-16
-
文件大小：4.81mb
-
已下载：0次
-
提 供 者：
-
相关连接：无下载说明：别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容来自于网络，使用问题请自行百度
自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。
1.echo uart,接收rx_data,再回复！
2.运行时请注意完整路径：
D:\EXP\EXP_SOPCbuilder\exp_micro_s
3.UART数据输入问题？
3.1 MODELSIM中w完信号后，run/restart一次。
3.2 设置clock=20ns。
3.3 命令行中输入uart_drive调出uart_in.log窗口。
+号后,输入LOVE CHINA！
3.4 run 1ms.看波形结果。
3.5 quit -f。
ZHJ
2009/11/9 晚-Quartus project file for Classic exp with MICRO-SEQUENCER:echo uart
1.echo uart,接收rx_data,再回复！
2.运行时请注意完整路径：
D:\EXP\EXP_SOPCbuilder\exp_micro_s
3.UART数据输入问题？
3.1 MODELSIM中w完信号后，run/restart一次。
3.2 设置clock=20ns。
3.3 命令行中输入uart_drive调出uart_in.log窗口。
+号后,输入LOVE CHINA！
3.4 run 1ms.看波形结果。
3.5 quit -f。
ZHJ
2009/11/9 晚-Quartus project file for Classic exp with MICRO-SEQUENCER:echo uart
(系统自动生成,下载前可以参看下载内容)
下载文件列表
exp_micro_s/microsequencer.mif
exp_micro_s/microsequencer.v.bak
exp_micro_s/exp_micro_s.qpf
exp_micro_s/exp_micro_s.qsf
exp_micro_s/sopc_builder_log.txt
exp_micro_s/microsequencer_hw.tcl
exp_micro_s/microsequencer.v
exp_micro_s/sopc_add_qip_file.tcl
exp_micro_s/MICRO.html
exp_micro_s/micro_seq.sopc
exp_micro_s/micro_seq.sopcinfo
exp_micro_s/micro_seq.html
exp_micro_s/microsequencer_0.v
exp_micro_s/micro_seq.qip
exp_micro_s/micro_seq.ptf
exp_micro_s/micro_seq.ptf.pre_generation_ptf
exp_micro_s/micro_seq.ptf.8.0
exp_micro_s/micro_seq.v
exp_micro_s/micro_seq.ptf.bak
exp_micro_s/micro_seq_log.txt
exp_micro_s/dma.v
exp_micro_s/onchip_memory.hex
exp_micro_s/onchip_memory.v
exp_micro_s/uart.v
exp_micro_s/micro_seq_inst.v
exp_micro_s/micro_seq.bsf
exp_micro_s/micro_seq_generation_script
exp_micro_s/microsequencer.ver
exp_micro_s/onchip_memory.ver
exp_micro_s/exp_micro_s.qws
exp_micro_s/micro_seq_sim/onchip_memory.dat
exp_micro_s/micro_seq_sim/contents_file_warning.txt
exp_micro_s/micro_seq_sim/uart_input_data_stream.dat
exp_micro_s/micro_seq_sim/uart_input_data_mutex.dat
exp_micro_s/micro_seq_sim/uart.pl
exp_micro_s/micro_seq_sim/tail-f.pl
exp_micro_s/micro_seq_sim/uart_log_module.txt
exp_micro_s/micro_seq_sim/virtuals.do
exp_micro_s/micro_seq_sim/wave_presets.do
exp_micro_s/micro_seq_sim/list_presets.do
exp_micro_s/micro_seq_sim/setup_sim.do
exp_micro_s/micro_seq_sim/uart_log.bat
exp_micro_s/micro_seq_sim/uart_drive.bat
exp_micro_s/micro_seq_sim/modelsim.tcl
exp_micro_s/micro_seq_sim/create_micro_seq_project.do
exp_micro_s/micro_seq_sim/transcript
exp_micro_s/micro_seq_sim/vsim.wlf
exp_micro_s/micro_seq_sim/wave.do
exp_micro_s/micro_seq_sim/uart_in.log
exp_micro_s/micro_seq_sim/micro_seq_sim.cr.mti
exp_micro_s/micro_seq_sim/micro_seq_sim.mpf
exp_micro_s/micro_seq_sim/modelsim.ini
exp_micro_s/micro_seq_sim/work/_info
exp_micro_s/micro_seq_sim/work/_vmake
exp_micro_s/micro_seq_sim/work/test_bench/_primary.vhd
exp_micro_s/micro_seq_sim/work/test_bench/verilog.psm
exp_micro_s/micro_seq_sim/work/test_bench/_primary.dbs
exp_micro_s/micro_seq_sim/work/test_bench/_primary.dat
exp_micro_s/micro_seq_sim/work/onchip_memory/_primary.vhd
exp_micro_s/micro_seq_sim/work/onchip_memory/verilog.psm
exp_micro_s/micro_seq_sim/work/onchip_memory/_primary.dbs
exp_micro_s/micro_seq_sim/work/onchip_memory/_primary.dat
exp_micro_s/micro_seq_sim/work/uart/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart/verilog.psm
exp_micro_s/micro_seq_sim/work/uart/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_regs/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_regs/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_regs/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_regs/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_rx/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_rx/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_rx/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_rx/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_tx/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_tx/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_tx/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_tx/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_log_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_log_module/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_log_module/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_log_module/_primary.dat
exp_micro_s/micro_seq_sim/work/dma/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma/verilog.psm
exp_micro_s/micro_seq_sim/work/dma/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_mem_write/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_mem_write/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_mem_write/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma_mem_write/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_mem_read/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_mem_read/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_mem_read/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma_mem_read/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_fifo_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_fifo_module/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_fifo_module/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma_fifo_module/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_fifo_module_fifo_ram_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_fifo_module_fifo_ram_module/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_
exp_micro_s/microsequencer.v.bak
exp_micro_s/exp_micro_s.qpf
exp_micro_s/exp_micro_s.qsf
exp_micro_s/sopc_builder_log.txt
exp_micro_s/microsequencer_hw.tcl
exp_micro_s/microsequencer.v
exp_micro_s/sopc_add_qip_file.tcl
exp_micro_s/MICRO.html
exp_micro_s/micro_seq.sopc
exp_micro_s/micro_seq.sopcinfo
exp_micro_s/micro_seq.html
exp_micro_s/microsequencer_0.v
exp_micro_s/micro_seq.qip
exp_micro_s/micro_seq.ptf
exp_micro_s/micro_seq.ptf.pre_generation_ptf
exp_micro_s/micro_seq.ptf.8.0
exp_micro_s/micro_seq.v
exp_micro_s/micro_seq.ptf.bak
exp_micro_s/micro_seq_log.txt
exp_micro_s/dma.v
exp_micro_s/onchip_memory.hex
exp_micro_s/onchip_memory.v
exp_micro_s/uart.v
exp_micro_s/micro_seq_inst.v
exp_micro_s/micro_seq.bsf
exp_micro_s/micro_seq_generation_script
exp_micro_s/microsequencer.ver
exp_micro_s/onchip_memory.ver
exp_micro_s/exp_micro_s.qws
exp_micro_s/micro_seq_sim/onchip_memory.dat
exp_micro_s/micro_seq_sim/contents_file_warning.txt
exp_micro_s/micro_seq_sim/uart_input_data_stream.dat
exp_micro_s/micro_seq_sim/uart_input_data_mutex.dat
exp_micro_s/micro_seq_sim/uart.pl
exp_micro_s/micro_seq_sim/tail-f.pl
exp_micro_s/micro_seq_sim/uart_log_module.txt
exp_micro_s/micro_seq_sim/virtuals.do
exp_micro_s/micro_seq_sim/wave_presets.do
exp_micro_s/micro_seq_sim/list_presets.do
exp_micro_s/micro_seq_sim/setup_sim.do
exp_micro_s/micro_seq_sim/uart_log.bat
exp_micro_s/micro_seq_sim/uart_drive.bat
exp_micro_s/micro_seq_sim/modelsim.tcl
exp_micro_s/micro_seq_sim/create_micro_seq_project.do
exp_micro_s/micro_seq_sim/transcript
exp_micro_s/micro_seq_sim/vsim.wlf
exp_micro_s/micro_seq_sim/wave.do
exp_micro_s/micro_seq_sim/uart_in.log
exp_micro_s/micro_seq_sim/micro_seq_sim.cr.mti
exp_micro_s/micro_seq_sim/micro_seq_sim.mpf
exp_micro_s/micro_seq_sim/modelsim.ini
exp_micro_s/micro_seq_sim/work/_info
exp_micro_s/micro_seq_sim/work/_vmake
exp_micro_s/micro_seq_sim/work/test_bench/_primary.vhd
exp_micro_s/micro_seq_sim/work/test_bench/verilog.psm
exp_micro_s/micro_seq_sim/work/test_bench/_primary.dbs
exp_micro_s/micro_seq_sim/work/test_bench/_primary.dat
exp_micro_s/micro_seq_sim/work/onchip_memory/_primary.vhd
exp_micro_s/micro_seq_sim/work/onchip_memory/verilog.psm
exp_micro_s/micro_seq_sim/work/onchip_memory/_primary.dbs
exp_micro_s/micro_seq_sim/work/onchip_memory/_primary.dat
exp_micro_s/micro_seq_sim/work/uart/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart/verilog.psm
exp_micro_s/micro_seq_sim/work/uart/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_regs/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_regs/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_regs/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_regs/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_rx/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_rx/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_rx/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_rx/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_rx_stimulus_source_character_source_rom_module/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_tx/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_tx/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_tx/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_tx/_primary.dat
exp_micro_s/micro_seq_sim/work/uart_log_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/uart_log_module/verilog.psm
exp_micro_s/micro_seq_sim/work/uart_log_module/_primary.dbs
exp_micro_s/micro_seq_sim/work/uart_log_module/_primary.dat
exp_micro_s/micro_seq_sim/work/dma/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma/verilog.psm
exp_micro_s/micro_seq_sim/work/dma/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_mem_write/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_mem_write/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_mem_write/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma_mem_write/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_mem_read/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_mem_read/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_mem_read/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma_mem_read/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_fifo_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_fifo_module/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_fifo_module/_primary.dbs
exp_micro_s/micro_seq_sim/work/dma_fifo_module/_primary.dat
exp_micro_s/micro_seq_sim/work/dma_fifo_module_fifo_ram_module/_primary.vhd
exp_micro_s/micro_seq_sim/work/dma_fifo_module_fifo_ram_module/verilog.psm
exp_micro_s/micro_seq_sim/work/dma_
本网站为编程资源及源代码搜集、介绍的搜索网站，版权归原作者所有！ 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.