文件名称:XAPP454
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所属分类:
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- 上传时间:2012-11-16
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文件大小:194.34kb
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已下载:0次
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Spartan3a MIG user interface
(系统自动生成,下载前可以参看下载内容)
下载文件列表
464/verilog/
464/verilog/par/
464/verilog/par/ddr2_test.ucf
464/verilog/rtl/
464/verilog/rtl/addr_gen.v
464/verilog/rtl/cal_ctl.v
464/verilog/rtl/cal_top.v
464/verilog/rtl/clk_dcm.v
464/verilog/rtl/cmd_fsm.v
464/verilog/rtl/cmp_data.v
464/verilog/rtl/controller.v
464/verilog/rtl/controller_iobs.v
464/verilog/rtl/data_path.v
464/verilog/rtl/data_path_iobs.v
464/verilog/rtl/data_path_rst.v
464/verilog/rtl/data_read.v
464/verilog/rtl/data_read_controller.v
464/verilog/rtl/data_write.v
464/verilog/rtl/ddr2_dm.v
464/verilog/rtl/ddr2_test.v
464/verilog/rtl/ddr2_test_bench.v
464/verilog/rtl/ddr2_top.v
464/verilog/rtl/defines.v
464/verilog/rtl/dqs_delay.v
464/verilog/rtl/fifo_0_wr_en.v
464/verilog/rtl/fifo_1_wr_en.v
464/verilog/rtl/glbl.v
464/verilog/rtl/infrastructure.v
464/verilog/rtl/infrastructure_iobs.v
464/verilog/rtl/iobs.v
464/verilog/rtl/lfsr32.v
464/verilog/rtl/mybufg.v
464/verilog/rtl/prem.v
464/verilog/rtl/rd_gray_ctr.v
464/verilog/rtl/r_w_dly.v
464/verilog/rtl/s3_ddr_iob.v
464/verilog/rtl/s3_dqs_iob.v
464/verilog/rtl/spartan3.v
464/verilog/rtl/tap_dly.v
464/verilog/rtl/wr_gray_ctr.v
464/verilog/synth/
464/verilog/synth/ddr1_test.prj
464/vhdl/
464/vhdl/par/
464/vhdl/par/ddr2_test.ucf
464/vhdl/rtl/
464/vhdl/rtl/addr_gen.vhd
464/vhdl/rtl/cal_ctl.vhd
464/vhdl/rtl/cal_top.vhd
464/vhdl/rtl/clk_dcm.vhd
464/vhdl/rtl/cmd_fsm.vhd
464/vhdl/rtl/cmp_data.vhd
464/vhdl/rtl/cntrl_display.vhd
464/vhdl/rtl/controller.vhd
464/vhdl/rtl/controller_iobs.vhd
464/vhdl/rtl/datapath_iobs.vhd
464/vhdl/rtl/data_path.vhd
464/vhdl/rtl/data_path_rst.vhd
464/vhdl/rtl/data_read.vhd
464/vhdl/rtl/data_read_controller.vhd
464/vhdl/rtl/data_write.vhd
464/vhdl/rtl/ddr2_dm.vhd
464/vhdl/rtl/ddr2_dqs_div.vhd
464/vhdl/rtl/ddr2_test.vhd
464/vhdl/rtl/ddr2_test_bench.vhd
464/vhdl/rtl/ddr2_top.vhd
464/vhdl/rtl/dqs_delay.vhd
464/vhdl/rtl/fifo_0_wr_en.vhd
464/vhdl/rtl/fifo_1_wr_en.vhd
464/vhdl/rtl/glbl.v
464/vhdl/rtl/infrastructure.vhd
464/vhdl/rtl/infrastructure_iobs.vhd
464/vhdl/rtl/iobs.vhd
464/vhdl/rtl/lfsr32.vhd
464/vhdl/rtl/mybufg.vhd
464/vhdl/rtl/parameter.vhd
464/vhdl/rtl/rd_gray_cntr.vhd
464/vhdl/rtl/r_w_dly.vhd
464/vhdl/rtl/s3_ddr_iob.vhd
464/vhdl/rtl/s3_dqs_iob.vhd
464/vhdl/rtl/spartan3.v
464/vhdl/rtl/spartan3.vhd
464/vhdl/rtl/tap_dly.vhd
464/vhdl/rtl/wr_gray_cntr.vhd
464/vhdl/synth/
464/vhdl/synth/ddr1_test.prj
464/
464/verilog/par/
464/verilog/par/ddr2_test.ucf
464/verilog/rtl/
464/verilog/rtl/addr_gen.v
464/verilog/rtl/cal_ctl.v
464/verilog/rtl/cal_top.v
464/verilog/rtl/clk_dcm.v
464/verilog/rtl/cmd_fsm.v
464/verilog/rtl/cmp_data.v
464/verilog/rtl/controller.v
464/verilog/rtl/controller_iobs.v
464/verilog/rtl/data_path.v
464/verilog/rtl/data_path_iobs.v
464/verilog/rtl/data_path_rst.v
464/verilog/rtl/data_read.v
464/verilog/rtl/data_read_controller.v
464/verilog/rtl/data_write.v
464/verilog/rtl/ddr2_dm.v
464/verilog/rtl/ddr2_test.v
464/verilog/rtl/ddr2_test_bench.v
464/verilog/rtl/ddr2_top.v
464/verilog/rtl/defines.v
464/verilog/rtl/dqs_delay.v
464/verilog/rtl/fifo_0_wr_en.v
464/verilog/rtl/fifo_1_wr_en.v
464/verilog/rtl/glbl.v
464/verilog/rtl/infrastructure.v
464/verilog/rtl/infrastructure_iobs.v
464/verilog/rtl/iobs.v
464/verilog/rtl/lfsr32.v
464/verilog/rtl/mybufg.v
464/verilog/rtl/prem.v
464/verilog/rtl/rd_gray_ctr.v
464/verilog/rtl/r_w_dly.v
464/verilog/rtl/s3_ddr_iob.v
464/verilog/rtl/s3_dqs_iob.v
464/verilog/rtl/spartan3.v
464/verilog/rtl/tap_dly.v
464/verilog/rtl/wr_gray_ctr.v
464/verilog/synth/
464/verilog/synth/ddr1_test.prj
464/vhdl/
464/vhdl/par/
464/vhdl/par/ddr2_test.ucf
464/vhdl/rtl/
464/vhdl/rtl/addr_gen.vhd
464/vhdl/rtl/cal_ctl.vhd
464/vhdl/rtl/cal_top.vhd
464/vhdl/rtl/clk_dcm.vhd
464/vhdl/rtl/cmd_fsm.vhd
464/vhdl/rtl/cmp_data.vhd
464/vhdl/rtl/cntrl_display.vhd
464/vhdl/rtl/controller.vhd
464/vhdl/rtl/controller_iobs.vhd
464/vhdl/rtl/datapath_iobs.vhd
464/vhdl/rtl/data_path.vhd
464/vhdl/rtl/data_path_rst.vhd
464/vhdl/rtl/data_read.vhd
464/vhdl/rtl/data_read_controller.vhd
464/vhdl/rtl/data_write.vhd
464/vhdl/rtl/ddr2_dm.vhd
464/vhdl/rtl/ddr2_dqs_div.vhd
464/vhdl/rtl/ddr2_test.vhd
464/vhdl/rtl/ddr2_test_bench.vhd
464/vhdl/rtl/ddr2_top.vhd
464/vhdl/rtl/dqs_delay.vhd
464/vhdl/rtl/fifo_0_wr_en.vhd
464/vhdl/rtl/fifo_1_wr_en.vhd
464/vhdl/rtl/glbl.v
464/vhdl/rtl/infrastructure.vhd
464/vhdl/rtl/infrastructure_iobs.vhd
464/vhdl/rtl/iobs.vhd
464/vhdl/rtl/lfsr32.vhd
464/vhdl/rtl/mybufg.vhd
464/vhdl/rtl/parameter.vhd
464/vhdl/rtl/rd_gray_cntr.vhd
464/vhdl/rtl/r_w_dly.vhd
464/vhdl/rtl/s3_ddr_iob.vhd
464/vhdl/rtl/s3_dqs_iob.vhd
464/vhdl/rtl/spartan3.v
464/vhdl/rtl/spartan3.vhd
464/vhdl/rtl/tap_dly.vhd
464/vhdl/rtl/wr_gray_cntr.vhd
464/vhdl/synth/
464/vhdl/synth/ddr1_test.prj
464/
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