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文件名称:i2c_master_slave_core_latest.tar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    4.35mb
  • 已下载：
    0次
  • 提 供 者：
    And***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave.

VMM Test-bench is also available.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

i2c_master_slave_core/
i2c_master_slave_core/tags/
i2c_master_slave_core/tags/t2/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/doc/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/doc/i2c_spec.pdf
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/doc/i2c_spec.doc
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/doc/i2c_core_verification_plan.pdf
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/verilog/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/verilog/rtl/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/verilog/rtl/counter.v
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/verilog/rtl/controller_interface.v
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/verilog/rtl/i2c_blk.v
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/verilog/rtl/shift.v
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/verilog/rtl/ms_core.v
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_interface.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_scenario_generator.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_top.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_monitor.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_slave_driver.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_scenario_packet.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_env.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_scoreboard.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_stimulus_packet.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_program_test.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_data_packet.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_mon_pkt.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_driver.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_reg_pkt.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_callback.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_clkgen.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_program1_test.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/config.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_coverage.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/vmm_i2c_sb_pkt.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/vmm_svtb/sb_callback.sv
i2c_master_slave_core/tags/t2/i2c_master_slave_core/i2c_master_slave_core/svtb/Readme
i2c_master_slave_core/tags/t1/
i2c_master_slave_core/tags/t1/i2c_master_slave_core/
i2c_master_slave_core/tags/t1/i2c_master_slave_core/doc/
i2c_master_slave_core/tags/t1/i2c_master_slave_core/doc/i2c_spec.pdf
i2c_master_slave_core/tags/t1/i2c_master_slave_core/doc/i2c_spec.doc
i2c_master_slave_core/tags/t1/i2c_master_slave_core/verilog/
i2c_master_slave_core/tags/t1/i2c_master_slave_core/verilog/rtl/
i2c_master_slave_core/tags/t1/i2c_master_slave_core/verilog/rtl/counter.v
i2c_master_slave_core/tags/t1/i2c_master_slave_core/verilog/rtl/controller_interface.v
i2c_master_slave_core/tags/t1/i2c_master_slave_core/verilog/rtl/i2c_blk.v
i2c_master_slave_core/tags/t1/i2c_master_slave_core/verilog/rtl/shift.v
i2c_master_slave_core/tags/t1/i2c_master_slave_core/verilog/rtl/ms_core.v
i2c_master_slave_core/branches/
i2c_master_slave_core/trunk/
i2c_master_slave_core/trunk/i2c_master_slave_core/
i2c_master_slave_core/trunk/i2c_master_slave_core/i2c_master_slave_core/
i2c_master_slave_core/trunk/i2c_master_slave_core/i2c_master_slave_core/doc/
i2c_master_slave_core/trunk/i2c_master_slave_core/i2c_master_slave_core/doc/i2c_spec.pdf
i2c_master_slave_core/trunk/i2c_master_slave_core/i2c_master_slave_core/doc/i2c_spec.doc
i2c_master_slave_core/trunk/i2c_master_slave_core/i2c_master_slave_core/doc/i2c_core_verification_plan.pdf
i2c_master_slave_core/trun

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