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文件名称:ddr_cntl_a_withtb

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    2008-10-13
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    2.28mb
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arm控制FPGA的DDR测试代码,共享一下-arm control FPGA DDR test code sharing what
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下载文件列表

ddr_cntl_a_withtb/bin/kdvm264024000.bin
ddr_cntl_a_withtb/bin/kdvm264024000.prm
ddr_cntl_a_withtb/bin/kdvm264024000.sig
ddr_cntl_a_withtb/bin
ddr_cntl_a_withtb/datasheet.txt
ddr_cntl_a_withtb/ddr_cntl_a.bgn
ddr_cntl_a_withtb/ddr_cntl_a.bit
ddr_cntl_a_withtb/ddr_cntl_a.bld
ddr_cntl_a_withtb/ddr_cntl_a.cel
ddr_cntl_a_withtb/ddr_cntl_a.cmd_log
ddr_cntl_a_withtb/ddr_cntl_a.drc
ddr_cntl_a_withtb/ddr_cntl_a.lfp
ddr_cntl_a_withtb/ddr_cntl_a.lso
ddr_cntl_a_withtb/ddr_cntl_a.ncd
ddr_cntl_a_withtb/ddr_cntl_a.ngc
ddr_cntl_a_withtb/ddr_cntl_a.ngd
ddr_cntl_a_withtb/ddr_cntl_a.ngr
ddr_cntl_a_withtb/ddr_cntl_a.pad
ddr_cntl_a_withtb/ddr_cntl_a.par
ddr_cntl_a_withtb/ddr_cntl_a.pcf
ddr_cntl_a_withtb/ddr_cntl_a.prj
ddr_cntl_a_withtb/ddr_cntl_a.stx
ddr_cntl_a_withtb/ddr_cntl_a.syr
ddr_cntl_a_withtb/ddr_cntl_a.twr
ddr_cntl_a_withtb/ddr_cntl_a.twx
ddr_cntl_a_withtb/ddr_cntl_a.ucf
ddr_cntl_a_withtb/ddr_cntl_a.unroutes
ddr_cntl_a_withtb/ddr_cntl_a.ut
ddr_cntl_a_withtb/ddr_cntl_a.v
ddr_cntl_a_withtb/ddr_cntl_a.xpi
ddr_cntl_a_withtb/ddr_cntl_a.xst
ddr_cntl_a_withtb/ddr_cntl_a_addr_gen_0.v
ddr_cntl_a_withtb/ddr_cntl_a_cal_ctl_0.v
ddr_cntl_a_withtb/ddr_cntl_a_cal_top.v
ddr_cntl_a_withtb/ddr_cntl_a_clk_dcm.v
ddr_cntl_a_withtb/ddr_cntl_a_cmd_fsm_0.v
ddr_cntl_a_withtb/ddr_cntl_a_cmp_data_0.v
ddr_cntl_a_withtb/ddr_cntl_a_controller_0.v
ddr_cntl_a_withtb/ddr_cntl_a_controller_iobs_0.v
ddr_cntl_a_withtb/ddr_cntl_a_data_path_0.v
ddr_cntl_a_withtb/ddr_cntl_a_data_path_iobs_0.v
ddr_cntl_a_withtb/ddr_cntl_a_data_path_rst.v
ddr_cntl_a_withtb/ddr_cntl_a_data_read_0.v
ddr_cntl_a_withtb/ddr_cntl_a_data_read_controller_0.v
ddr_cntl_a_withtb/ddr_cntl_a_data_write_0.v
ddr_cntl_a_withtb/ddr_cntl_a_ddr1_dm_0.v
ddr_cntl_a_withtb/ddr_cntl_a_ddr1_test_bench_0.v
ddr_cntl_a_withtb/ddr_cntl_a_dqs_delay.v
ddr_cntl_a_withtb/ddr_cntl_a_fifo_0_wr_en_0.v
ddr_cntl_a_withtb/ddr_cntl_a_fifo_1_wr_en_0.v
ddr_cntl_a_withtb/ddr_cntl_a_fpga_editor.log
ddr_cntl_a_withtb/ddr_cntl_a_glbl.v
ddr_cntl_a_withtb/ddr_cntl_a_infrastructure.v
ddr_cntl_a_withtb/ddr_cntl_a_infrastructure_iobs_0.v
ddr_cntl_a_withtb/ddr_cntl_a_infrastructure_top.v
ddr_cntl_a_withtb/ddr_cntl_a_iobs_0.v
ddr_cntl_a_withtb/ddr_cntl_a_last_par.ncd
ddr_cntl_a_withtb/ddr_cntl_a_lfsr32_0.v
ddr_cntl_a_withtb/ddr_cntl_a_main_0.v
ddr_cntl_a_withtb/ddr_cntl_a_map.mrp
ddr_cntl_a_withtb/ddr_cntl_a_map.ncd
ddr_cntl_a_withtb/ddr_cntl_a_map.ngm
ddr_cntl_a_withtb/ddr_cntl_a_mybufg_0.v
ddr_cntl_a_withtb/ddr_cntl_a_pad.csv
ddr_cntl_a_withtb/ddr_cntl_a_pad.txt
ddr_cntl_a_withtb/ddr_cntl_a_parameters_0.v
ddr_cntl_a_withtb/ddr_cntl_a_RAM8D_0.v
ddr_cntl_a_withtb/ddr_cntl_a_rd_gray_cntr.v
ddr_cntl_a_withtb/ddr_cntl_a_s3_ddr_iob.v
ddr_cntl_a_withtb/ddr_cntl_a_s3_dqs_iob.v
ddr_cntl_a_withtb/ddr_cntl_a_summary.html
ddr_cntl_a_withtb/ddr_cntl_a_tap_dly_0.v
ddr_cntl_a_withtb/ddr_cntl_a_top_0.v
ddr_cntl_a_withtb/ddr_cntl_a_vhdl.prj
ddr_cntl_a_withtb/ddr_cntl_a_withtb.ipf
ddr_cntl_a_withtb/ddr_cntl_a_withtb.ise
ddr_cntl_a_withtb/ddr_cntl_a_withtb.ise_ISE_Backup
ddr_cntl_a_withtb/ddr_cntl_a_wr_gray_cntr.v
ddr_cntl_a_withtb/ddr_cntl_a_xmdf.tcl
ddr_cntl_a_withtb/docs/768c.pdf
ddr_cntl_a_withtb/docs/adr_cntrl_timingsheet_0.xls
ddr_cntl_a_withtb/docs/read_timingsheet_0.xls
ddr_cntl_a_withtb/docs/write_timingsheet_0.xls
ddr_cntl_a_withtb/docs
ddr_cntl_a_withtb/KDVM264024000.bin
ddr_cntl_a_withtb/KDVM264024000.prm
ddr_cntl_a_withtb/KDVM264024000.sig
ddr_cntl_a_withtb/log.txt
ddr_cntl_a_withtb/mig.prj
ddr_cntl_a_withtb/par/ddr_cntl_a.ucf
ddr_cntl_a_withtb/par/ise_flow.bat
ddr_cntl_a_withtb/par/ise_run.txt
ddr_cntl_a_withtb/par/mem_interface_top.ut
ddr_cntl_a_withtb/par
ddr_cntl_a_withtb/rtl/ddr_cntl_a.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_addr_gen_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_cal_ctl_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_cal_top.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_clk_dcm.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_cmd_fsm_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_cmp_data_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_controller_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_controller_iobs_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_path_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_path_iobs_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_path_rst.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_read_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_read_controller_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_write_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_ddr1_dm_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_ddr1_test_bench_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_dqs_delay.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_fifo_0_wr_en_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_fifo_1_wr_en_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_glbl.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_infrastructure.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_infrastructure_iobs_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_infrastructure_top.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_iobs_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_lfsr32_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_main_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_mybufg_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_parameters_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_RAM8D_0.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_rd_gray_cntr.v
ddr_cntl_a_withtb/rtl/ddr_cntl_a_s3_ddr_iob.v
ddr_cntl_a_wit

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